There are two aspects to burst mode in a DRAM : its internal organisation, and the requirements of the system it's installed in. The latter has changed over time, but the former is substantially the same as original DRAM.
Internally, DRAM is arranged as a 2-D array of tiny capacitors, and accessing DRAM is a two step process.
- In the first step, (Row Access) you read an entire row - 256 bits up to maybe 4096 bits, depending on the generation of DRAM - into a small internal memory (really a register) which holds the entire row.
- In the second step, (Column Access) you select one or more bits from that register, and access them via the device pins. This is a relatively fast operation as data is now in a register.
- A third stage happens transparently, called Precharge, where the entire row is written back to the 2-D array, including any data written in step 2. (This is even necessary if no writes occurred, as Stage 1 drained some charge from that row of tiny capacitors, and you want to fully restore the charge to prevent corrupting memory).
Now the second step may be repeated practically any number of times, very fast, without the penalty of having to repeat the Row Access or Precharge steps. (There is an upper limit, in the hundreds of Column Access periods, imposed by the temporarily weak charge on the capacitors, but we can ignore this for now).
Burst Mode uses this feature to transfer bits as fast as you can clock data in or out, for bits close to the first one you accessed.
And this is where Burst Size comes in, with different DRAMs to meet different system requirements.
Most DRAM is installed in high performance microprocessor systems, and one of the tricks used in these processors to increase performance is cache memory.
Cache is a small (and very fast) memory, which holds a copy of recently used data because you are likely to need it again, and don't want to repeat the slow process of fetching from DRAM. It is usually organised as small chunks of memory, maybe 8 words (or 16 or 32) called cache lines; cache design (line size, number of lines, etc) is extensively tweaked to maximise measured performance on whatever tests the designers think are important.
Now consider your program wants to read address 1043, which isn't in cache at the moment, and the cache line size is 8 words, so the cache line covers words 1040..1047. (I'm ignoring bits per word, just assume each word takes one bit from our DRAM chip here).
The cache manager issues a Read for address 1043, with Burst Size = 8, so that it can fill a cache line with a single Burst transfer.
The DRAM will see:
- a Row Access for Address 1000 covering 1000..10FF.
- a Column Access for address 43 within the row
- Eight Data Strobes, which will return data from locations 43, 44,45,46,47,40,41,42 ensuring the requested word is read first, and the entire cache line is filled (note the address wraps round to 40).
This is only an example scheme. Burst Length and the address wraparound is negotiated after powerup, by writing the DRAM's configuration register along with Row Access times etc. This is described in excruciating detail in data sheets for your specific DRAM, and vary between devices (specifically between generations like SDRAM, DDR, DDR3 etc).
Other schemes are possible : way back when, DRAM was also used for video controllers, and the best hack read an entire Row out to serve as a video line, or for ultra fast video processing. DRAMs that can do that support "Page Mode" transfers of any length up to 256,512 bits etc.
Page Mode lived up until SDRAM but not DDR (though it may live on in specialist VRAM - Video RAM) so if you need it in DDR you have to fake it with a carefully timed sequence of Column Accesses at whatever Burst Size it supports.
(It was also fantastic for streaming high speed data into an FPGA for custom processing; sadly that got a bit more difficult with newer DDRx DRAMs)