I am currently working with real-time image processing in FGPA. I have some timing problems about the classical FFT algorithm. i.e : FFT of one images spends more time than one frame period time. I dont get the term of burst-size(or length) of a SDRAM.Is this a mode of SDRAM ( aka Burst-mode? ). I am using DDR3.

Best Regards,

Edit: PART is MT41K256M16. This DDR3 works in 1866 Megatransfer/second datarate. Below image credit : Micron, MT41K256M16 enter image description here

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    \$\begingroup\$ Google "ddr burst size" gives you 200.000 hits. \$\endgroup\$
    – Oldfart
    Jan 13 '18 at 12:06
  • \$\begingroup\$ Depending on the processing involved, DDR(x) can be very slow. Most of the image processing I have done used flowthrough memory. \$\endgroup\$ Jan 13 '18 at 13:40
  • \$\begingroup\$ What Bandwidth do you need? \$\endgroup\$ Jan 13 '18 at 14:05
  • \$\begingroup\$ Image is 720*1280 @60Hz \$\endgroup\$
    – doner_t
    Jan 13 '18 at 14:54
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    \$\begingroup\$ The burst size is the maximum number of bits you can store before the package explodes and spills all the bits. \$\endgroup\$ Jan 13 '18 at 16:16

There are two aspects to burst mode in a DRAM : its internal organisation, and the requirements of the system it's installed in. The latter has changed over time, but the former is substantially the same as original DRAM.

Internally, DRAM is arranged as a 2-D array of tiny capacitors, and accessing DRAM is a two step process.

  • In the first step, (Row Access) you read an entire row - 256 bits up to maybe 4096 bits, depending on the generation of DRAM - into a small internal memory (really a register) which holds the entire row.
  • In the second step, (Column Access) you select one or more bits from that register, and access them via the device pins. This is a relatively fast operation as data is now in a register.
  • A third stage happens transparently, called Precharge, where the entire row is written back to the 2-D array, including any data written in step 2. (This is even necessary if no writes occurred, as Stage 1 drained some charge from that row of tiny capacitors, and you want to fully restore the charge to prevent corrupting memory).

Now the second step may be repeated practically any number of times, very fast, without the penalty of having to repeat the Row Access or Precharge steps. (There is an upper limit, in the hundreds of Column Access periods, imposed by the temporarily weak charge on the capacitors, but we can ignore this for now).

Burst Mode uses this feature to transfer bits as fast as you can clock data in or out, for bits close to the first one you accessed.

And this is where Burst Size comes in, with different DRAMs to meet different system requirements.

Most DRAM is installed in high performance microprocessor systems, and one of the tricks used in these processors to increase performance is cache memory.

Cache is a small (and very fast) memory, which holds a copy of recently used data because you are likely to need it again, and don't want to repeat the slow process of fetching from DRAM. It is usually organised as small chunks of memory, maybe 8 words (or 16 or 32) called cache lines; cache design (line size, number of lines, etc) is extensively tweaked to maximise measured performance on whatever tests the designers think are important.

Now consider your program wants to read address 1043, which isn't in cache at the moment, and the cache line size is 8 words, so the cache line covers words 1040..1047. (I'm ignoring bits per word, just assume each word takes one bit from our DRAM chip here).

The cache manager issues a Read for address 1043, with Burst Size = 8, so that it can fill a cache line with a single Burst transfer.

The DRAM will see:

  • a Row Access for Address 1000 covering 1000..10FF.
  • a Column Access for address 43 within the row
  • Eight Data Strobes, which will return data from locations 43, 44,45,46,47,40,41,42 ensuring the requested word is read first, and the entire cache line is filled (note the address wraps round to 40).

This is only an example scheme. Burst Length and the address wraparound is negotiated after powerup, by writing the DRAM's configuration register along with Row Access times etc. This is described in excruciating detail in data sheets for your specific DRAM, and vary between devices (specifically between generations like SDRAM, DDR, DDR3 etc).

Other schemes are possible : way back when, DRAM was also used for video controllers, and the best hack read an entire Row out to serve as a video line, or for ultra fast video processing. DRAMs that can do that support "Page Mode" transfers of any length up to 256,512 bits etc.

Page Mode lived up until SDRAM but not DDR (though it may live on in specialist VRAM - Video RAM) so if you need it in DDR you have to fake it with a carefully timed sequence of Column Accesses at whatever Burst Size it supports.

(It was also fantastic for streaming high speed data into an FPGA for custom processing; sadly that got a bit more difficult with newer DDRx DRAMs)

  • \$\begingroup\$ Dear @Brian Drummond, Thank you for reply. I wonder that how are stored a 720*1280 , 16-bit images into the DDR3 memory banks (My DDR3 has 64-bit data-width)? i.e. : a DMA sends image pixel data to DDR3 as line-by-line. 1. line, 2.line,...., 720.line are sent to DDR3 memory, successively. \$\endgroup\$
    – doner_t
    Jan 13 '18 at 15:30
  • \$\begingroup\$ You'll need to read your FPGA code to find that out. \$\endgroup\$ Jan 13 '18 at 15:52
  • \$\begingroup\$ Dear @Brian Drummond, It is Xilinx' s Memory Interface Generator(MIG) IP, located between a VideoDMA and 64-bit DDR3 memory. I will try. \$\endgroup\$
    – doner_t
    Jan 13 '18 at 16:11
  • \$\begingroup\$ MIG is fairly low tech (last time I looked at it), but fortunately supplied as source code. As supplied, performance was poor. I had to modify it to simulate "page mode" style of operation with carefully timed "Burst Mode" transfers - and to delay Refresh operations (stop them interfering with real work) but guarantee none were missed. It was not easy but worked well in the end. \$\endgroup\$ Jan 13 '18 at 16:46
  • \$\begingroup\$ Dear @Brian Drummond, I still do not understand difference between 'Page Mode' and 'Burst Mode'of an SDRAM. \$\endgroup\$
    – doner_t
    Jan 13 '18 at 16:55

DDR achieves its interface speed using bursts or consecutive delivery or writing of data at the next address without needing to supply new the new address or setup internally. So you, the controller, setup the address you want to read or write from and then on the following cycles the memory chip will read the data at that address and say the data at the next eight addresses (in its bank and row). It can do this without having received any new information from you.

Now it can burst or quickly send those 8 pieces of data to you. Setting up a new address takes time as the ddr chip has to maybe open a new bank or the row. So in this way they save all that time and can achieve the ddr interface speed.

There are even things people do like interleaving to try to hide the address and fetch latency even further at the system level.

You can see how this would mean trying to use ddr as random access memory hitting small pieces of information stored all over the place would be much slower than the maximum interface speed.

  • \$\begingroup\$ Dear @Some Hardware Guy, thank you. Say, I have a 512 MB DDR3 RAM that its data-width is 64-bit. And its burst size is 8. ( I think this is 8-byte). Then, does it mean that, in a write transaction, 8-byte -8 byte is writing to DDR3 memory? \$\endgroup\$
    – doner_t
    Jan 13 '18 at 15:03

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