Whereas we have instructions such as LDAX B , LDAX D !!!
As @Finbarr said, data pointed by the register pair HL is mnemonically treated differently than
BC. There're two things to consider in the scope of the question:
1. Why word
LDAX and what does it mean?
LDAX is just a mnemonic, and set of characters corresponding to the specific CPU opcode. In general, it could have been anything developers wanted, distinct from other mnemonics to differentiate with other CPU operations. LD most probably means load and A means accumulator. What X stands for should be indirect. Why not LDAI you would ask? This is actually a good question, and most probably developers of assembler mnemonics wanted differentiation with
To understand it better you must look into the history of Intel 8-bit processors, their opcodes and mnemonics used. The set of related CPUs are 8008 -> 8080 -> 8085 and fork to Z80. There was specific instruction set in 8008, and developers were trying to extend it to 8080 and then to 8085. Z80 is different story, it has its own set of mnemonics, very similar to the 8080's, but different, without this
8008 allowed indirect load only from one register pair -
HL, and it was called register
M. When accessing this register CPU was actually accessing external memory at the address set in CPU register pair
HL. There were no other indirect registers, thus
M seemed to be the good choice standing for memory.
8080 is an extension to 8008, and now it allows loading accumulator from memory address pointed by register pairs DE and BC, however what would be the virtual register to use in mnemonic? M1? M2? MD? MB? And developers decided, for new 8080 CPU opcodes, to introduce new commands eliminating confusion and make code designed for 8080 look similar/portable to 8008, thus assembly mnemonics set of 8080 being a superset of 8008, and not new set.
In contrast, in Z80 assembler all indirect access is made uniform, and programmers explicitly state which register pair is used: e.g.
LD A,(DE) and
LD A,(BC), and machine code generated by the compiler will be the same to
LDAX D and
LDAX B respectively.
2. Why HL is not in the list of LDAX?
First, for compatibility reasons with the 8008/8080 assembler; second reason is that
(HL)) has real functional reason to exist. There're a number of operations, when CPU uses its RAM logically the same way as its internal registers, thus
M functionally is really one more register addressed by the pair
HL. These commands are (in mnemonic):
ORA M and
INR M. Its opcode is
00_110_100, where leading
00 and trailing
100 define operation to increment contents of the 8-bit register, and
100 in the middle is identification of indirect access of the RAM using HL register. So, opcode
00_111_100 corresponds to
INR A (
111 identifies accumulator register) and opcode
00_001_100 corresponds to
INR C (
001 identifies register C).
LDAX H exists in the processor, and its opcode is the same as
MOV A,M, but your assembler may not (or - to your surprise may!) accept this mnemonic.