I started designing a simple 4 port USB hub based around the FE1.1S IC. Using the datasheet, I managed to connect connections to almost all the pins... but there are some that confuse me. Schematic included at the end.

  • Is the EEprom necessary, and if so, what IC should I use?
  • What voltage do the status LEDs receive?
  • Do I use a voltage divider or a linear regulator for the three voltage levels required on pins VDD5, VD33, VD18? (I have put in two voltage dividers for the time being)
  • What do I need to do for pins VD18_O and VD33_O?
  • Why does the datasheet say for pin REXT (14) that I need to "A 2.7KΩ (± 1%) resister should be connected to VSS to provide internal bias reference.", Do I have to connect a resistor between REXT and VSS?
  • What other connections and components do I need on the other pins to get the hub functional?

Schematic: Schematic

Also, Here is the PCB design that I have in mind:


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    – Dave Tweed
    Jan 15, 2018 at 15:17

2 Answers 2


This is all in the datasheet if you know where to look.

That IC has internal voltage regulators for the 1.8V and 3.3V supplies (this is what the VD18_O and VD33_O pins do).
So connect VD18_O to VD18 (along with the recommended 10uF cap) and the same for VD33 & VD33_O.
Get rid of those voltage dividers - they have no place in this circuit.

Apparently the EEPROM is used to store "Vendor ID, Product ID, & Device Release Number and Number of Downstream Ports" and the data layout is specified on page 7.
However the note at the end of the paragraph indicates that the IC has a set of defaults which it uses if the EEPROM data is invalid, so you may be able to get away with leaving the EEPROM off.

The LEDs are digital outputs and the datasheet only specifies the minimum voltage swing on those pins as 0.4V (for low) to 2.4V (for high). A low could be closer to 0V and a high could be closer to Vdd5 though.

As for Rext on pin-14: just do as you're told - fit a 2k7 and call it done.

Other pins:

  • I would pull XRSTJ up to Vdd5 - probably with a 1k resistor
  • BUSJ needs to be pulled either high or low depending on if your hub is bus powered or self-powered
  • pull TEST low as the datasheet tells you
  • ignore PWRJ since you're not switching your downstream ports
  • 1
    \$\begingroup\$ Yeah, I know it's all in there in the datasheet, but I find it difficult to understand, it's my first time doing a project like this... How would I connect the two capacitors? The positive end to the connections between the two sets of pins, and negatives to ground? \$\endgroup\$
    – skillz21
    Jan 15, 2018 at 15:40
  • \$\begingroup\$ Yes, just like that. \$\endgroup\$
    – brhans
    Jan 15, 2018 at 16:31
  • 1
    \$\begingroup\$ The datasheet describes EEPROM content. But the EEPROM has I2C interface, and therefore must have some slave address, which the datasheet omitted to mention. Strong chances are that this should be a 24C02 type of EEPROM, because this is what typically is used. But typically the IC should operate without any EEPROM. \$\endgroup\$ Jan 15, 2018 at 17:07

The datasheet of this particular chip lacks several design details that you can find in the FE2.1 datasheet, which is from the same family of products but offers 7 downstream USB ports.

Now then, as it was said before, the chip includes both 3.3V and 1.8V LDO internal regulators. That means there's no need for a volage divider to feed that part of the circuit, but we do still need a voltage divider for another purpose.

  • "VBUSM" pin monitors the V+ line of the upstream USB port. For safety reasons the use of this pin is mandatory if the devices is bus powered. The problem is that we can't connect it directly to 5V as the chip operates on a 3.3 voltage level, to do that, we need a voltage divider. The values suggested by the manufacturer for this divider are 47K for R1 and 100K for R2, which creates an output of around 3.4 volts with an output impedance of 31.9K ohms.

  • "REXT" pin creates an internal voltage reference for the chip internals. Use a 2.7K 1% tolerance resistor to connect it to ground.

  • "XRSTJ" will reset the chip when pulled low. Connect this pin to 5V with a 100K resistor to avoid a reset loop.

  • "TEST" pin is only present in the LQFP package, and it should be pulled low for regular operation.

  • "BUSJ" acts as a bus power indicator to the chip. When pulled up to 5V with a 100K resistor, it tells the chip the hub is "Self Powered", and when pulled down to ground with a 10K resistor, it tells the chip the hub is "Bus Powered". The manufacturer indicates there's a third way to combine both states, but it's considered unsafe.

  • "VDD5" is a 5V input for the 3.3V LDO. Then, the 3.3V LDO output is connected to the input of a 1.8V LDO. The outputs of these LDOs are connected to "VD33_O" and "VD18_0". They should be wired to "VD33" and "VD18" respectively. Each power line needs a 10uF decoupling capacitor.

  • "PWRJ" is an output pin intended for Ganged Power Switching (Downstream ports overcurrent protection). If you choose to implement this protection in your circuit, it works as follows: When "OVCJ" input pin is pulled low, PWRJ will be pulled up. This signaling scheme is compatible with most electronical switches. If you don't want to include this protection in your circuit, leave PWRJ floating and connect OVCJ to 3V3.

  • The EEPROM is optional if you want to provide custom device information. If you choose to not include an EEPROM and operate the chip with the default descriptors, leave "TESTJ" pin floating.

  • LED1 and LED2 high voltage can be anywhere from 2V to 5V. Connect them through a 330 ohm resistor to avoid over current.

This chip has a lot to offer, but it has some flaws, one being the lack of information on the chip and the cheap LDOs with usually terrible tolerances that are used inside of the chip.

Here's the Self Powered recommended application.


USB6 is used as a power input.

If you want to create a Bus Powered hub, leave USB6, C9 and R5 out, connect USB5 VCC to the 5V line, swap C4, C5, C6, C7, and C8 with 2.2uF capacitors and pull BUSJ low with a 10K resistor.

Theres a third way to configure the chip to use both Bus Powered and Self Powered modes, but it caused instability when I tested it. Nonetheless, it was used in the official demo board. To do this third configuration, connect USB5 VCC to the circuit through a 2A 220 Ohm Ferrite Bead. Fine tune C8 and then connect VDD5 to 5V through a low forward voltage Schotkky Barrier Diode with the cathode facing the 5V net. Remember to pull BUSJ up with a 100k resistor.

  • \$\begingroup\$ Well here the crappy datasheet conundrum grows. According to the FE2.1 datasheet, TESTJ can be left NC as it has an internal pull-up, but the FE1.1s doesn't specify any inputs as having internal pull-up/down resistors and says to tie it to ground for regular operation. We're left with the question, "did they make real changes on the FE2.1 or just munge two FE1.1 dies together?" Anyway, probably best to obey the FE1.1s datasheet here. \$\endgroup\$ Jun 30, 2020 at 1:42
  • \$\begingroup\$ In FE1.1s Pin TEST (only LQFP package Pin 40) is something different as Pin TESTJ (LQFP pin 2 / SSOP pin 27). Pin TEST have to be tied to GND, whereas TESTJ have an internal pull-up and can be left open \$\endgroup\$
    – Achim
    May 13, 2022 at 20:29

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