# Packing register pairs on Lattice FPGA slice. How?

On my design (Lattice MachXO2 FPGA) I use a lot of registers set by a signal and reset by another (both synchronous with the clock), like this:

process(Clk)
if rising_edge(Clk) then
if set_condition = '1' then
flag <= '1';
elsif reset_condition = '1' then
flag <= '0';
end if;
end if;
end process


This is synthesized into a register (flag) with its CE and D inputs driven by one LUT each. I also tried code like this:

process(Clk)
if rising_edge(Clk) then
o1 <= i1;
end if;
end process;
i1 <= '1' when set_condition = '1' else
'0' when reset_condition = '1' else o1;


This is synthesized into a register (flag) with its LSR being driven by the set signal and the D input being driven by one LUT as a feedback mux. Since the FPGA is allocated by slices and each has two LUT4s and two registers, both implementations share a common problem (for me) in that they use the register control inputs, which are common to both. This prevents using the second register on a slice for another purpose, wasting it and causing my design to fail mapping for lack of slices (I have around 80% of registers used, 90% of LUT4s and 103% of slices).

To resolve this I tested a component-instatiated feedback mux solution that uses a single LUT to drive the input of the register, without using the CE or LSR inputs. To verify the solution I've tested with two registers (only one shown below), that should be packed on a single slice. But they are not, each register uses its own slice.

d1: FD1S3AX
port map
(
CK => Clk,
D => i1,
Q => o1
);
l1: LUT4
generic map
(
INIT => b"1111_0010_0011_0010"
)
port map
(
A => High,
B => En1,
C => Dis1,
D => o1,
Z => i1
);


I've since found a partial solution, by adding LOCATE commands to the LPF file. By doing so I can get two registers into the same slice but I have to name the slice, locking it into place on the FPGA fabric.

LOCATE COMP "d1" SITE "R3C40A";
LOCATE COMP "d2" SITE "R3C40A";
LOCATE COMP "i1" SITE "R3C40A";
LOCATE COMP "i2" SITE "R3C40A";


Since I don't want to P&R the entire design by hand is there a way to group pairs of LUTs and regs together on the same slice but allowing them to float across the entire device ?

## 1 Answer

If you want an asynchronous reset, separated for each registers, it's probably impossible since both registers share a single LSR input.

If you are looking for synchronous operations only, as your code show, you could try some of the latches primitives form this library. That would make synthesis unambiguous and map directly to a hardware latch without extra logic or constraints.

Another options is to make a script that generate placement constraint files for you. I did for some timing circuit with microsemi's tools, it can be easy if you have repetitive structures. I had plenty of margin on resources so I'm not sure if that could work for you.

• I've updated the question with partial code for my component-instantiated attempt (using the library you mentioned) which still was mapped to two slices, can't understand why. Everything is indeed synchronous. – Carlos Azevedo Jan 16 '18 at 11:13