# Serial resistance for SPI bus (33 ohms, 50 ohms....)

I have a question about SPI communication. I learnt that we should place a 33 or 50 ohms serial resistance in MOSI/MISO lines for the adaption, and overshot. My question is how could we find these values (33 or 50 ohms)?

I want to calculate it. I have a little knowledge in transmission line, but I never see the proof.

Could you say how to find it?

• I think this depends a lot on the speed you're running at. I also suspect that if you needed to do it on MOSI and MISO you'd need it on SCLK too. Can't say it's something I ever needed to do, but I've never run an SPI bus at 50MHz. Commented Jan 16, 2018 at 13:27
• Yes you're right. On SCLK too. I forgot
– Tack
Commented Jan 16, 2018 at 15:02
• As a side note, I did not see others mentioning it. You must put series resistor as close to signal source as possible. Not in the middle of conductor and not near the receiver! Commented Jan 17, 2018 at 17:02

The general idea is that the bus has a particular characteristic impedance, typically in the range of 50-70Ω, but the driver output impedance is usually much lower, more like 15-30Ω.

The series resistance is selected to bring the total source impedance up to match that of the bus in order to eliminate reflections at that end.

Since you frequently don't know either impedance very precisely, some trial and error may be required to find the best termination value.

• So if I'm not wrong: Z_line = 50-70Ω Z_Output = 15-30Ω. Z_R_added =50-70Ω - 15-30Ω. Z_R_added =55-20Ω Right?
– Tack
Commented Jan 16, 2018 at 15:03

## Proposals

Proposals like, put 100nF on the VCC, or put 33 Ohms on the communication line are mostly not based on a basic understanding of what's really happening. That's mainly the reason why the "lesson" helped you and you basically learned nothing.

## Reflection, Impedance trimming

Putting a resistor in series or parallel does affect the impedance the endpoints (your SPI-Master and SPI-Slave) see. That resistance depends a lot on the environment like the wave impedance on the PCB and the output-/input impedance. If the impedance is mismatched, some unpleasant effects show up on your connection (reflection, over- under-shoot).

But normally an SPI connection is almost DC, since the bus speed is at the lower MHz.

Because the SPI bus contains pulses for data and clock, those have sharp edges which cause frequencies even above your clock speed.

(Have a look at: https://en.wikipedia.org/wiki/Square_wave#Fourier_analysis)

Sharp edges lead to short rise-times which lead to high frequencies causing the problems mentioned above.

### For a rule of thumb:

You don't care about that (higher-level) problems when length of the SPI bus is less then the critical length:

$l_{crit} \approx 3 cm \cdot t_{rise}$

[risetime in nano seconds]

## To come back to your question

When putting a resistor on a typical SPI connection, you do not need to care about the wave impendance, but you need to get rid of the transients coming from the sharp edges and the resistor helps to smooth them out.

The SPI master must charge the input capacitance on the receivers and with a higher impedance on the bus lines, you get an load curve. It is like an RC low-pass filter, provide the resistance.

## Now, what R to choose?

To select the correct resistance, have look on the capacitance of your bus. If you can not get it from datasheets, you need to measure your SPI bus. What you want is at least a stable signal level on the data line on the rising edge (or falling edge [depending on your SPI mode]) of the clock. Almost every IC with SPI interface specifies the maximum rise-time for the clock. So, you can "trim" your setup near to that level.

For that, starting with 33 Ohms is a good starting point.

My intent was to tell you what happens on the line, when putting a resistor on it.

• Re: "You care [...] when length of the SPI bus is less then the critical length" Shouldn't that be that you don't care with the short SPI bus, since it usually doesn't need to be treated as a transmission line in that case? Commented Jan 16, 2018 at 14:59
• I'm interesting in that, because I usually put 100 nF on VCC... And i'm trying to know why this values. From where did you take the critical length? If I have 100 ns as maximal rise-time, how can I choose my resistance?
– Tack
Commented Jan 16, 2018 at 15:26
• 100nF have been the first suitable ceramic condensators on market. That's where it comes from. In our applications most of the time we use 1µF ceramics, because they are cheap, have low esr and can supply peak current for logic components. Tau is R*C on a simple RC low-pass. The rise-time is approx 2.2 time Tau. Hope that helps Commented Jan 16, 2018 at 16:05
• I was asking about the 2.2*tau. Is it come from V(t)=V0(1-exp(-t/tau)). From 10% to 90% rise time, we have ln(0.9)-ln(0.1) = 2.197 ? tr=2.2*RC with R, the value I'm looking for, the output capacitance, and tr the maximal rise time clock?
– Tack
Commented Jan 16, 2018 at 17:08
• C the overall capacity Commented Jan 16, 2018 at 20:13