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Every time I read something about RAS e CAS there are mentions to the "DRAM" word. The only difference that comes in mind is the presence of a latch/counter and registers in case of the DRAM. However I suppose that they can be both organized in a Row x Column fashion and use the same logic that is: select and read a row and extract a word (a set of columns) from that row.

So why are the RAS and CAS signal only used for a DRAM and not for a SRAM ?

How would a memory like this be implemented using SRAM ?

enter image description here

(This is a 32M x 8 DRAM chip)

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    \$\begingroup\$ Is your question "How SRAM works?" ? \$\endgroup\$ – Eugene Sh. Jan 16 '18 at 14:54
  • \$\begingroup\$ No. I know that the memory cells are implemented differently in SRAM and DRAM (CMOS inverter vs trench capacitor). The question is about how can a DRAM row-column logic be implemented using an SRAM and if RAS and CAS signals are needed. \$\endgroup\$ – Bemipefe Jan 16 '18 at 15:24
  • \$\begingroup\$ You will need a controller decoding the row and column signals/addresses into a linear address suitable for feeding into SRAM. It is not straightforward. Maybe you can find some off-the-shelf... \$\endgroup\$ – Eugene Sh. Jan 16 '18 at 15:29
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Both Static and Dynamic RAMs contain arrays of memory cells with rows and columns, and in theory, there's nothing to stop you from implementing a Static RAM using a multiplexed address bus and hence needing the RAS/CAS signals to manage access. But in practice, nobody does this for two main reasons:

  • The vastly greater complexity of an SRAM cell means that SRAM chips have much less storage than DRAM chips and there is no great saving to be achieved in multiplexing the address lines because there aren't as many of them.

  • SRAM is often used when a faster speed is needed than can be achieved with DRAM, such as on-chip caches, and the use of a multiplexed address bus would slow down the memory and lose most of the advantage of using SRAM.

RAS and CAS are also used by the refresh process required by DRAM where a whole row is refreshed at a time. The row address can be supplied externally in some refresh modes while the column address remains latched.

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SRAM does not normally use a multiplexed address bus. If you want to drive one from an interface intended for DRAM, you'll have to do the demultiplexing externally. RAS and CAS will be used to enable latches that hold the address bits for the duration of the memory cycle. CAS will also be used to enable the SRAM chip after all of the address bits are stable.

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