Every time I read something about RAS e CAS there are mentions to the "DRAM" word. The only difference that comes in mind is the presence of a latch/counter and registers in case of the DRAM. However I suppose that they can be both organized in a Row x Column fashion and use the same logic that is: select and read a row and extract a word (a set of columns) from that row.
So why are the RAS and CAS signal only used for a DRAM and not for a SRAM ?
How would a memory like this be implemented using SRAM ?
(This is a 32M x 8 DRAM chip)