Do I really need a level-shifter if I use 5 V-powered devices on an I2C-bus that has pull-ups to 3.3 V?

In my understanding the devices will only pull the lines (SDA, SCL) low (to ground) and never drive their supply-voltage to the bus. So I don't see a reason for a level-shifter as long as all devices detect the voltage from the pull-ups (3.3 V) as logical high. That should be the case with devices using 5 V as supply.

In my case I have an IC whose inputs are not 5 V-tolerant as master and I could power my slaves with 3.3 V but using 5 V is easier in my circuit and allows higher (internal) clock-rates for the slaves.

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    \$\begingroup\$ So to sum things up: - No chip is in danger when using devices with 5V as Vdd on a I2C-bus using pull-ups to 3.3V - It may or may not work, depending on tolerances, internal chip design, ... \$\endgroup\$
    – Jannis
    Jul 5 '12 at 10:50
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    \$\begingroup\$ Correct - no danger of damage, just no guarantee of correct operation. \$\endgroup\$ Jul 5 '12 at 11:23

According to version 4 of the \$\mathrm{I^2C}\$ spec,

"Due to the variety of different technology devices (CMOS, NMOS, bipolar) that can be connected to the I2C-bus, the levels of the logical ‘0’ (LOW) and ‘1’ (HIGH) are not fixed and depend on the associated level of VDD. Input reference levels are set as 30 % and 70 % of VDD; VIL is 0.3VDD and VIH is 0.7VDD. See Figure 38, timing diagram. Some legacy device input levels were fixed at VIL = 1.5 V and VIH = 3.0 V, but all new devices require this 30 %/70 % specification. See Section 6 for electrical specifications." (page 9)

Deeper in the spec, you'll see that this \$ 0.7 \times V_{DD}\$ is the minimum logic high voltage:

excerpt from NXP I2C spec rev. 4

For your 5V system:

\$ 0.7 \times 5 V = 3.5 V\$

\$ 0.3 \times 5 V = 1.5 V\$

To me, the 3.3 V pull-up looks marginal, especially if any of your 5V devices use the 'new' standard of \$ 0.7 \times V_{DD}\$ for logic HIGH.

Your mileage may vary, but it's always best to be within the spec wherever possible...

  • \$\begingroup\$ Thanks for the cleanup stevenvh. I was rushing yesterday. \$\endgroup\$ Jul 5 '12 at 11:25

Cees's answer is incorrect, in particular the "always" and "any". Microcontroller I/Os may need 0.6 Vdd as a minimum for a high level, other have a minimum of 0.7 Vdd, and like Madmanguruman indicates this is the standard for I2C. 0.7 Vdd is 3.5 V at a 5 V supply, so 3.3 V is already too low.

But it's even worse. Voltage regulators often have a 5 % tolerance on their nominal output voltage, so worst case 5 V may be 5.25 V, and then 0.7 Vdd becomes 3.675 V. Minimum input for a high level. If the 3.3 V has a negative 5 % tolerance then 3.3 V becomes 3.135 V. So with tolerances taken into account the input may well be half a volt too low, or 15 %.


So I don't see a reason for a level-shifter as long as all devices detect the voltage from the pull-ups (3.3V) as logical high. That should be the case with devices using 5V as supply.

is an untimely conclusion. Always check datasheets and do the calculation.


This is a pretty old question, and many points were discussed already. However, none of the answers here mention the incorrect assumption that in I2C

the devices will only pull the lines (..) and never drive

In fact, in one of I2C modes, the HighSpeed mode, the master device can actively drive the bus, so if you're considering allowing HS communication over the bus, then mixing voltages might a bad idea:

  • High-speed IC devices are downward compatible allowing for mixed bus systems.
  • In order to shorten signal rise time HS mode master devices have a combination of an open-drain pull-down and current-source pull-up circuit on the SCL output.
  • HS IC masters can actually source current to the bus which is referred to as boosting.
  • This current source is enabled only (!) during HS operation and just for one master.

Citation comes from an introduction to the HS mode which I've just found here. Highlights added by me.


I feel that the other answers didn't really answer Jannis' question. He asked about using 5V devices on a 3.3V bus (presumably 3.3V MCU). I agree that having the pull-ups tied to 3.3V will be okay, e.g. safe for the master device, since the SDA/SCL pins will only pull down, as he mentioned. Beware that the slaves and master will need to share a common ground (Vss pins equipotential) in order to protect the MCU from overvoltage, but this was probably going to be the case anyway. So Jannis' method should work, without a level shifter.

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    \$\begingroup\$ Welcome!! I noticed you are a new contributor, so you might not have realized that you are providing an answer to a question is more than six years old. The system constantly brings up old questions so that these are revised, you should keep that in mind. \$\endgroup\$ Nov 12 '18 at 20:35
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    \$\begingroup\$ What's wrong about providing an answer to an old question? The answer might not be helpful for the person who created the question, but it will be useful for other people looking for answers to the same question. If an answer adds some new information is welcome, even if it answers very old questions. \$\endgroup\$ Dec 16 '20 at 16:46
  • \$\begingroup\$ This answer doesn't add anything to answers already posted; and in fact is incorrect. Jannis' method is unlikely to work, due to I²C's idiosyncratic definition of "high" as being ≥70% VDD. It won't cause damage, but - as I can attest from recent experience! - it will result in erratic behaviour. Downvoted. \$\endgroup\$ Sep 14 at 9:35

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