I am working at an FGPA shop right now using Xilinx FPGAs. I do not have a ton of experience with designing logic, especially when it comes to microprocessors. One of the big movements my team is looking at is to adopt High Level Synthesis (HLS) which translates an algorithm written in C down to RTL that can then be placed and routed onto an FPGA or even forwarded to an ASIC design.
A similar question was asked here Convert C to FPGA, but I want to direct the response of this question directly to the architecture of a microprocessor.
My question is what would it take to implement an algorithm for a microprocessor? You obviously have the ISA, so I am assuming the your inputs would be each operand, depending on how many your processor takes, and the op code? I am assuming there would need to be some buffer allocated to represent the caches/registers for the architecture? Also, you would probably need to allocate space for RAM since ISAs have register indirect operations that might require those type of memories to be already allocated.
For example, lets say I want to make an Intel 8008. Can you give me pseudocode to demonstrate the algorithm that can be put through a high level synthesizer to get that hardware?
When I ask for pseudo code I obviously do not mean a full product. I just want the major steps that would be involved in the design of the algorithm. I am guessing it would revolve around fetching, decoding, and executing the input to the function. The comments with the emulators and the AUGH look like they will be a big help.