I'm trying to create a circuit diagram that corresponds to the Mealy diagram I created for the following problem, but I'm not sure how many flip-flops I should use.
A data stream receives serial data of 1 bit, synchronised by a clock pulse. Create a Mealy State Diagram that:
- Starts from an initial state (IS).
xy = 01when it recognises the bit-sequence
1001and returns to IS.
xy = 10when it recognises the bit-sequence
011and returns to IS.
- In any other case, the system should return
xy = 00.
Mealy Diagram (Corrected):
(This is the diagram I came up with)
Based on the Mealy diagram above, I would say 3 flip-flops are needed, because
100 needs 3 bits to be represented. Is there, however, a way to implement it with less? If so, why?