To check the synthesisability of while loop, I created one hypothetical vhdl code as follows.

library IEEE;

entity test_loop is
Port ( a : in  INTEGER;
       i : in INTEGER;
       CLK : in std_logic;
       b : out  unsigned (3 downto 0)); 
end test_loop;

architecture Behavioral of test_loop is
  --signal C : unsigned (3 downto 0) := "0000";
    variable C : unsigned (3 downto 0) := "0000";
    if (rising_edge(CLK)) then
      while(a /= i ) loop
        C := C + 1;
      end loop;
      b <= C;
    end if;
  end process;
end Behavioral;

I was expecting a synthesising error because I think the loop has no definite bounds. I cant simulate this code too because it goes infinite for a /= i . But surprisingly this code got synthesised in Xilinx 13.1 ISE without showing errors. What might be the reason ?


changed C into variable. Still the code is getting synthesised. RTL view is obtained as -

enter image description here

  • 3
    \$\begingroup\$ Because C is a signal not a variable. See the difference between signal assignment semantics and variable assignment semantics. \$\endgroup\$
    – user16324
    Jan 17, 2018 at 14:26
  • 1
    \$\begingroup\$ @Brian. I changed the signal C to variable and used variable assignment. But it still got synthesised without errors. \$\endgroup\$ Jan 17, 2018 at 14:39
  • 4
    \$\begingroup\$ Well that's ... interesting. If you posted the code as code, I might have tried it in ISE14.4. But I can't compile your picture. Too bad. \$\endgroup\$
    – user16324
    Jan 17, 2018 at 14:47
  • 2
    \$\begingroup\$ I generally recommend for beginners to not use loops or variables. The semantics of how they work in VHDL is very confusing to someone coming from C or other programming languages. \$\endgroup\$
    – kjgregory
    Jan 17, 2018 at 14:50
  • 2
    \$\begingroup\$ "Oh then it has to be some problem with my Xilinx 13.1 !??" Very likely. That version is ancient. There are petrified trees younger than that. \$\endgroup\$
    – Oldfart
    Jan 17, 2018 at 15:02

1 Answer 1


With the help of the comments under the post, it has been confirmed that it's nothing but a bug in Xilinx 13.1 ISE. Seems like it uses old buggy compilers depending on the chosen FPGA. The above code is not synthesisable as I expected. The code was not synthesised in newer versions like ISE 14.4 and Vivado. It threw non-static loop limit exceeded error as the loop condition has no definite bounds.

  • 2
    \$\begingroup\$ Xilinx Synthesis Technology (XST) User guide under XST VHDL Language Support, VHDL Constructs Supported in XST, VHDL Statements, the table VHDL Loop Statements, you'd only find two loop statement constructs with a while loop conspicuously missing. Referring to IEEE Std 1076.6-2004 (RTL Synthesis) still in effect for identical language in 11.3 in 2009, while loops aren't suppored for synthesis (8.8.9 Loop statement). The XST UG layout matches Clause 8. Syntax from 1076.6). There was no expectation while loops would synthesize. 14.7 XST supports while loops for newer devices (Brian's Spartan-6). \$\endgroup\$
    – user8352
    Jan 18, 2018 at 19:08

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