While loop in VHDL

To check the synthesisability of while loop, I created one hypothetical vhdl code as follows.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.all;

entity test_loop is
Port ( a : in  INTEGER;
i : in INTEGER;
CLK : in std_logic;
b : out  unsigned (3 downto 0));
end test_loop;

architecture Behavioral of test_loop is
--signal C : unsigned (3 downto 0) := "0000";
begin
process(CLK)
variable C : unsigned (3 downto 0) := "0000";
begin
if (rising_edge(CLK)) then
while(a /= i ) loop
C := C + 1;
end loop;
b <= C;
end if;
end process;
end Behavioral;


I was expecting a synthesising error because I think the loop has no definite bounds. I cant simulate this code too because it goes infinite for a /= i . But surprisingly this code got synthesised in Xilinx 13.1 ISE without showing errors. What might be the reason ?

UPDATED:

changed C into variable. Still the code is getting synthesised. RTL view is obtained as -

• Because C is a signal not a variable. See the difference between signal assignment semantics and variable assignment semantics. – Brian Drummond Jan 17 '18 at 14:26
• @Brian. I changed the signal C to variable and used variable assignment. But it still got synthesised without errors. – Meenie Leis Jan 17 '18 at 14:39
• Well that's ... interesting. If you posted the code as code, I might have tried it in ISE14.4. But I can't compile your picture. Too bad. – Brian Drummond Jan 17 '18 at 14:47
• I generally recommend for beginners to not use loops or variables. The semantics of how they work in VHDL is very confusing to someone coming from C or other programming languages. – kjgregory Jan 17 '18 at 14:50
• "Oh then it has to be some problem with my Xilinx 13.1 !??" Very likely. That version is ancient. There are petrified trees younger than that. – Oldfart Jan 17 '18 at 15:02