0
\$\begingroup\$

I built an PCB board housing a couple of ICs and the PCB communicates with a PC over USB with a Saxo board (contains FX2 USB controller and Cyclone FPGA). The Saxo board sits on my PCB as daugther board and is powered via USB.

The FPGA's I/O is 3.3V which I want to convert to 1V. Hence I use a logic level shifter, namely ADG3308 from Analog Devices.

Now consider the following setup:

  1. The PCB is completely powered off. All connections disabled (except for the Saxo Board)
  2. The Saxo board is powered via USB and sets one I/O pin to high (3.3V).

In an isolated sense, this means I have an ADG3308 with only 3.3V supplied at an I/O pin (say, Y1). VCCA and VCCY (the supplies of the ADG3308) are connected to the circuit but the supplies are off.

Now the following strange observation: Measuring VCCY, it is actually 2.7V! This can only happen through driving the I/O pin!

But: VCCY is supposed to be connected to a 3.3V benchtop supply and there is a connection to an on-board voltage regulator that generates 1V (and 1.2V). Lo and behold, VCCA (which is the output of this voltage regulator) is also 1V. Which means that the 3.3V I/O pin drives the VCCY pin of the ADG with 2.7V which is enough for the 1.0 and 1.2 regulators to work.

Furthermore, more ICs (which require the 1V supply) are pretty functional! In total they would draw about 60mA from the benchtop supply!

Question 1: Can it really be that the single I/O pin of the FPGA drives the complete PCB - indirectly - sinking tons of mAs?

Question 2: Is this a problem? Bug/Feature? Does it have implications about a startup sequence? I feel not quite comfortable driving the whole PCB with an I/O pin over the USB interface. That would mean that I want to power on first before I connect USB. But this seems not like something "normal" to do.

Clearly, ground is shared between the PCB and the saxo board (and hence USB) but no supply is shared.

Here is a sketch to facilitate understanding (red: measured voltages):

PCB Sketch

\$\endgroup\$
  • 3
    \$\begingroup\$ Some microcontrollers with ESD diodes will forward bias and power the microcontroller when the I/O pin has power applied, even if the VCC pins are not. If this is what you are seeing, you may be damaging the board doing that. \$\endgroup\$ – Ron Beyer Jan 18 '18 at 3:50
  • \$\begingroup\$ So regarding Q2: So I should make sure to apply power first and then connect via USB? I can do this with my board .... but how would I do it for a lil more reliable solution? \$\endgroup\$ – divB Jan 18 '18 at 5:08
  • 1
    \$\begingroup\$ Providing an input voltage when the chip is unpowered is bad. Clearly, you violate the maximum ratings. You should at least provide power on VCCY when the saxo is on. But I don't even see any hints on the ADG datasheet indicating you can have one of the supplies off. So you're probably not even allowed to do that. You should choose a level translator that supports partial power down. Also, the min voltage for VCCA on ADG3308 is 1.15V. \$\endgroup\$ – dim Jan 18 '18 at 5:33
  • \$\begingroup\$ Good point! I took this over from a previous design - did not realize the 1.15V. Still works with 1V though. \$\endgroup\$ – divB Jan 18 '18 at 7:54
  • \$\begingroup\$ Regarding your Q2 sub-question: Yes, if the device functionality (or some max condition) is violated under different power-up sequences, the design should employ strictly-controlled power management and ensure the desired power-up sequencing. \$\endgroup\$ – Ale..chenski Jan 18 '18 at 15:02
1
\$\begingroup\$

Yes, this is a pretty standard situation when a low-power IC gets powerd via a GPIO pin. All (I repeat, ALL) CMOS circuits carry ESD prodection diodes , which clamp I/O pins to ground and IC's power rail, see this picture from EE News Automotive, as example:

enter image description here

When the main rail is not powered and floating with high impedance, a voltage from connected I/O pin will have the upper clamp diode in open state, and I/O voltage will leak into power rail up to input voltage minus 0.7V of the diode, making the IC sometimes fully operational.

To prevent this kind of problems, a passive "bleeding resistor" (rail to ground) is usually sufficient, or, if extra power is of concern, it should be controlled with active switch (FET).

\$\endgroup\$
  • 1
    \$\begingroup\$ DISCLAIMER: there are ESD clamping techniques that use "dynamic clamping", where the diodes are not DC tied to ground or Vcc but instead go to come special floating circuit connected only capacitively to power rails. These ICs don't have this back-voltage problem. \$\endgroup\$ – Ale..chenski Jan 18 '18 at 5:40
  • 2
    \$\begingroup\$ You should edit this information into your answer (without 'disclaimer'), not use a comment \$\endgroup\$ – TonyM Jan 18 '18 at 7:50
  • \$\begingroup\$ @TonyM, why include this info? We are not discussing why one chip gets leakage, while another doesn't. I added the Note for nit-pickers. \$\endgroup\$ – Ale..chenski Jan 18 '18 at 14:54
  • 1
    \$\begingroup\$ Don't understand the nit-picker/note/disclaimer stuff. It looks like a further part of your answer. Putting detail into Q's or A's is always better than drifting it in comments. Up to you, seemed reasonable, didn't think you'd object so hard... \$\endgroup\$ – TonyM Jan 18 '18 at 15:01

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.