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Let suppose a 256 bit memory controller is installed on a PCB with GDDR5 memory modules.

In normal mode you can split the lines into 8 group of 32 bit and drive 8 modules x 1Gbit (128 MB) = 1 GB of total frame buffer memory.

In clamshell mode you can split the lines into 16 group of 16 bit and drive 16 modules x 1Gbit (128 MB) = 2 GB of total frame buffer memory.

The question is: how is it possible to address 128 MB using only 16 bit?

Does it use multiplexed addresses?

What about the throughput, is it really the same on both configuration?

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    \$\begingroup\$ I've corrected several instances of "125 MB" to "128 MB" in your question. Keep in mind 1 GB of memory is 1024 MB (2^30 bytes), not 1000 MB (10^9 bytes). \$\endgroup\$ – duskwuff Jan 24 '18 at 19:27
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In normal mode you can split the lines into 8 group of 32 bit and drive 8 modules x 1Gbit (128 MB) = 1 GB of total frame buffer memory.

In clamshell mode you can split the lines into 16 group of 16 bit and drive 16 modules x 1Gbit (128 MB) = 2 GB of total frame buffer memory.

"The lines" that you're referring to here are lines of the data bus, not the address bus. The address bus is multiplexed in GDDR5 SGRAM.

In normal mode, each memory module has its own 32-bit data bus. In clamshell mode, the memory modules are grouped into pairs; in each pair, both modules share address (and control) signals, but have separate 16-bit data busses.

from Elpida "Introduction To GDDR5 SGRAM"

Since the combined width of all data busses is the same either way (256 bits), the throughput is identical.

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  • \$\begingroup\$ What does it imply having shared address signals ? Is the data stripped across every pair ? \$\endgroup\$ – Bemipefe Jan 26 '18 at 9:27
  • \$\begingroup\$ @Bemipefe Correct. In clamshell mode, each pair of memory modules is accessed in the same pattern, but reads/writes different data. \$\endgroup\$ – duskwuff Jan 27 '18 at 0:52

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