I am trying to find out what transformer is it, one of standard or a custom one and what specifications does it how (i.e. power ratio).

How would I go about finding that out?

I do not need exact answer, but more of a methodology.

The input is standard AC 100-240V 50/60Hz and output is DC 12V9A (as is specified on the schematics).


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    \$\begingroup\$ Find the person who designed the circuit and ask them what transformer they specified. \$\endgroup\$ – Colin Jan 18 '18 at 10:49
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    \$\begingroup\$ @Colin__s the circuit is from online, I don't even know where to start looking for whomever did this design. I think I have better chances figuring out transfer specs than finding who did this one. \$\endgroup\$ – user3352528 Jan 18 '18 at 10:50
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    \$\begingroup\$ Start with the datasheet for that IC in the lower left corner (UC3843C.) There may be an example in it that matches your circuit. \$\endgroup\$ – JRE Jan 18 '18 at 11:26
  • \$\begingroup\$ @JRE Yes, the TI documentation provides some insight as well as reference design for a different power output thought. \$\endgroup\$ – user3352528 Jan 19 '18 at 3:05

This is a difficult exercise and a precise answer is not obvious. First, regarding the turns ratio for the power winding. In the primary side, the drain voltage peaks to \$V_{in}+V_{clamp}\$ in which \$V_{clamp}\$ is the voltage across the \$RCD\$ clamping network. When you design such a converter, you know that the maximum allowable drain voltage in the worst-case situation (max input, output short circuit, overload etc.) shall not exceed the maximum drain voltage of the selected MOSFET to which you add a derating factor.

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Wise designers usually derate by 15% (\$k_d\$) meaning that for the 650-V type you have, the max observable drain voltage must remain below 552 V. If you consider a universal-input type of converter, then the max rectified voltage on the bulk capacitor is 374 V (considering 265 V rms as the max input). If you read the document presented here, you can see that the clamp voltage is selected according to this formula: \$V_{clamp}=BV_{DSS}k_d-V_{os}-V_{in}\$. For your 650-V transistor and providing we have wise designers :-), the clamp voltage should be 158 V. The \$V_{os}\$ term is the clamp voltage diode overshoot linked to its forward transit time and can be as high as 20 V or so.

Now that we have the hypothetical clamp voltage, you select another factor which is the amount of reflected voltage you accept in the primary side compared to the selected clamp voltage. You obviously want to stay away from the 158-V limit because as you approach it, you dangerously over dissipate in the resistance. The term \$k_c\$ tells you how far the reflected voltage stays away from the clamp value and links the reflected output voltage to the clamp voltage by: \$V_{clamp}\$>\$k_c\frac{V_{out}+V_f}{N}\$ meaning that \$N>\frac{k_c(V_{out}+V_f)}{V_{clamp}}\$. Considering the 12-V output, a 158-V clamp level, a 1-V output diode forward drop and a \$k_c\$ of 1.3, then \$N>1:0.107\$ (\$N_p:N_s\$) as a first swag estimation.

The second lead is the output diode. It must sustain a reverse voltage equal to \$NV_{in}+V_{out}\$. The diode is a 100-V type. For diodes, it truly depends on the designer experience. Some adopt 100% derating (a 100-V diode means the actual voltage is max 50 V) but some also choose 50% as they observe the max reverse voltage in worst-case conditions and damp all unwanted oscillations. In that case, for a 100-V diode, the max voltage is more 67 V. With a 374-V max input voltage, the turns ratio is obtained by solving \$NV_{in}+V_{out}=67\$ which implies a maximum \$N\$ equal to 0.147.

For the primary inductance, it is more complicated. The switching frequency considering the \$RC\$ on the RT/CT pin looks like it is 65 kHz, a very typical value for mains-operated switching converters. The maximum peak current is \$I_{peak,max}=\frac{1\;V}{0.22\;\Omega}=4.6\;A\$. Considering a 15% design margin, the operating peak \$I_p\$ is probably 3.8 A. Considering a CCM-operated flyback converter and a 0.18 turns ratio, the duty ratio is given by \$D=\frac{V_{out}}{V_{out}+NV_{in}}\approx 36\$% or an on-time of \$0.36\times15.4\;µs=5.5\;µs\$ at a 120-V dc input (85 V rms). The off-time is then 15.4-5.5=9.9 µs.

The average input power of this converter (considering an efficiency of 85%) is \$P_{in}=\frac{12\times8}{0.85}=113\;W\$ leading to an average input current of 941 mA. Then, I will use the inductor ripple current derived here and equal to \$\Delta I_L\approx \frac{T_{sw}V_{in}V_{out}}{L_p(V_{out}+NV_{in})}\$ in which \$L_p\$ is your unknown. The input current (the 941 mA) is linked to the ripple by \$I_{in}=(I_p-\frac{\Delta I_L}{2})D\$. Extract \$\Delta I_L\$ and equate it to the previous definition. Solve for \$L_p\$ and calculate \$L_p=\frac{DT_{sw}V_{in}V_{out}}{(V_{out}+NV_{in})2(DI_p-I_{in})}\approx 238\;µH\$. I'm done for the day! : )

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  • \$\begingroup\$ Thanks! That is the answer I was looking for - with detailed explanations on how to figure this out on my own (thanks for your calculations sheet too, will definitely help me in the future) \$\endgroup\$ – user3352528 Jan 19 '18 at 3:06
  • \$\begingroup\$ My pleasure if I could help. I presented one possible way to determine these values and designers may take another path. I slightly revised the \$N\$ value and updated the Mathcad sheet. \$\endgroup\$ – Verbal Kint Jan 19 '18 at 6:34
  • \$\begingroup\$ Thanks again. One thing I am confused about is that your calculations are based on Vin = 120V. Meanwhile the supply specs say that for any input between 100-240V (AC) it will output stable 12V8A (DC). How does that happen? Wouldn't on different input voltage the voltage on primary loop be different? Which would result in different voltage on secondary loop? Which in turn results in different voltage on output pins. Am I missing something? I feel like this is better off as a separate question perhaps. \$\endgroup\$ – user3352528 Jan 19 '18 at 7:28
  • \$\begingroup\$ The stress in voltage is the highest at the highest input line (265 V rms) but the stress in current is the largest at the lowest input (85 V rms or 120 V dc). Remember, the nominal spec is 100-240 V rms, but universal-mains designs must work down to 85 V rms. The loop stabilizes the output voltage versus \$V_{in}\$ and \$I_{out}\$. I've chosen low line for the inductance calculations because the converter is likely to operate in CCM at that input. Please have a look at the seminar I linked, plenty of good stuff in it : ) \$\endgroup\$ – Verbal Kint Jan 19 '18 at 7:36

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