# J/K to D type flip flop strange behaviour

As a student, I have been tasked in one of my assignments to design a traffic light system using D-Type flip flops, simulate it on Proteus, then build it on breadboard. This was simple enough, and after a half hour, the process was complete, and my circuit was working.

simulate this circuit – Schematic created using CircuitLab

In this case, the Flip Flops were D type, not T! (The schematic editor didnt have a D type with both Q and inverted Q output). I got the required output, which was to make the traffic lights go in the following order: R - R/A - G - A - R where R=RED, A=AMBER, G=GREEN, R/A=RED and AMBER

The next task seemed to be very simple too. It was to do the same thing, but use J/K flip flops instead. As far as I am aware, to turn a J/K flip flop into a D type, you place an inverter between the J and K pins:

Again, seems simple enough. I built the circuit on Proteus, and the circuit worked fine. It done exactly as I had asked. I then built it on breadboard, and it didn't work correctly. The lights went in the wrong order. It went R - A - G - R/A - R. So the RED/AMBER combination was in the wrong place.

I changed my proteus simulation to use the 74LS76 (the IC we were given) and to my surprise, the simulation started acting as my practical circuit, with the LEDs in the wrong order (I was originally using a generic J/K on Proteus). The only difference between the 2 was the 74LS76 has an inverted clock input, so I did a new simulation with an inverter on the clock input of the generic J/K and shared the clock line with the 74LS76 and when running the simulation, both flip flops acted exactly the same. So why would they be acting differently when put into the full circuit? I have been trying to figure it out for the best part of an hour now and no idea!

The task is really to design a state machine to implement the different states of the traffic lights and move between them in the correct sequence. For a state machine the flip flops should be all be clocked by the same signal, and the flip flop inputs set up so that the system moves from the current state to the next state when the clock edge arrives.

But instead, you've connected the /Q output of one to the CLK of the other, which is something you might get away with in some situations but not others, partly because there will be a short period when the system may go through a sort of incorrect intermediate state on its way to the correct one.

You then rather missed the point of using J-K flip flops instead of D-types by just trying to convert them into D-types using an inverter. J-K flip flops give you a lot more ability to control the output, and I'm guessing the point of the exercise is to get you to fully understand that and learn how to use them.

Also the 74LS76 is a master-slave device. As it states in the data sheet:

J-K input is loaded into the master while the clock is high and transferred to the slave on the high-to-low transition. For these devices the J and K inputs must be stable while the clock is high.

So you can't exactly convert them into D-type flip flops with an inverter anyway.

• Ahhh, thanks for the thorough answer! Flip flops aren't something I use regularly! I thought using the same circuit as the d type (after converting) would work. How come the master/slave device won't allow conversion to D but others will?
– MCG
Jan 19, 2018 at 11:31
• It will in some circumstances, provided you keep the inputs stable all the time the clock is high. A regular D-type just has setup and hold times to observe. Jan 19, 2018 at 11:47
• Would they not have time to stabilise before the next pulse? It's only going at 1Hz
– MCG
Jan 19, 2018 at 12:53