# Verilog: XOR all signals of vector together

Say I'm given a vector wire large_bus[63:0] of width 64. How can I XOR the individual signals together without writing them all out:

assign XOR_value = large_bus[0] ^ large_bus[1] ^ ... ^ large_bus[63] ?

I'm especially interested in doing this for vectors where the width is specified by a localparam.

reg [63:0] large_bus;