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Bistable multivibrator

I am trying to understand this circuit but as of yet I still have a number of gaps in my reasoning. So far I have deduced:

(assuming TR1 is ON and TR2 is OFF)

  • left hand side capacitor charges towards 0.2-Vcc since Vc1 (voltage at collector of TR1) is tied to 0.2V due to transistor being ON (if trigger input is at Vcc during steady state)
  • right hand side capacitor charges to a small voltage (difference between Vcc and the voltage at Vc2 (voltage at collector of TR2) which can be worked out using superposition is very small)
  • upon negative edge trigger bases at TR1 and TR2 are pulled down since capacitors cannot handle sudden changes in voltage -> hence D1 is turned ON thus turning OFF TR1 --> Vc1 is no longer tied to 0.2V, goes to approx Vcc thus turning on TR2, Vc2 is now 0.2V.

These are my gaps in reasoning:

  • What is the role of the 220K resistor?
  • How the capacitors charge/discharge, to what voltages, when do they stop charging/discharging?

thank you for your help!

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  • \$\begingroup\$ Please ask a specific question, you'll get better answers. This is a Q&A site after all \$\endgroup\$ – Voltage Spike Jan 19 '18 at 18:39
  • \$\begingroup\$ Have you tried simulating this circuit? \$\endgroup\$ – vofa Jan 19 '18 at 18:41
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Just for review, let's start with the following schematic. There are two BJT sections, with their outputs coupled to the opposite section's input via a resistor:

schematic

simulate this circuit – Schematic created using CircuitLab

In effect, each section is an inverter with a weak pull-down at the input. As connected, the circuit is bistable in the sense that if the left stage's input is taken as LOW, then its output is HIGH and forms the input for the right stage. Since the right stage has a HIGH input, it's output is LOW. This matches up with our assumption, so it is stable. We can work through the opposite logic and arrive at opposite but stable results. So while we cannot say which stable circumstance actually happens, we can say that it appears on the surface that some stable condition will result.

Slight variations in components and parasitics will probably determine which of the two stable situations results, if this were placed on a protoboard or otherwise wired up. But it should be fine.

On a more quantitative level, we can see that the voltage value of a LOW at the input of a stage will be about \$\frac{2}{3}V_{CE_{SAT}}\$. That will usually be \$\lt 200\:\text{mV}\$ with a series impedance of about \$32\:\text{k}\Omega\$. While not exactly reverse-biasing, this really should be low enough in order to keep the following BJT essentially "OFF". (There might be a tiny residual collector current enabled by this setup, but not enough to develop any meaningful voltage drop across its collector resistor.)

Similarly, the voltage value of a HIGH at the input of a stage will be about \$\frac{2}{3}V_{CC}\$ with a series impedance again of a very similar \$34\:\text{k}\Omega\$. The base current will therefore be about \$I_B=\frac{V_{CC}}{50\:\text{k}\Omega}\$. This implies that any \$\beta\ge \frac{50\:\text{k}\Omega}{3.9\:\text{k}\Omega}\approx 13\$ is sufficient here to allow a HIGH input to generate a fully LOW output.


Now, let's keep the above circuit in place and add in the new components:

schematic

simulate this circuit

(As your question suggests, the trigger signal is the low-going edge.)

What's been added, and why?

Well, both inputs have been coupled to the trigger pulse via a capacitor and diode. Start by thinking about the original circuit.

Without worrying the quantitative details, we know that the output of a stage will either be very close to ground or else it will be very close to \$V_{CC}\$. For purposes of our discussion, let's assume that the left stage of the circuit has its BJT "off" and so its output is close to \$V_{CC}\$. The right stage of the circuit has its BJT "on" and so its output is close to \$0\:\text{V}\$.

The input voltage at the base for the left stage (off) is about \$V_{B_1}\approx 200\:\text{mV}\$ (likely less.) The input voltage at the base for the right stage (on) is about \$V_{B_2}\approx 700\:\text{mV}\$ (thereabouts.)

The voltage across \$D_1\$ will reverse-bias it and \$C_1\$ will charge up only via \$R_7\$. The voltage across \$D_2\$ will be a forward-biased value of about \$500\:\text{mV}\$. Enough that there is a small current there loading its base and adding to the charging current into \$C_2\$. So \$C_2\$ will charge via both \$D_2\$ and also \$R_8\$.

We don't know the quiescent voltage at the trigger input, but let's call it \$V_{HI}\$ for now. (It will be low-going to some new voltage called \$V_{LO}\$ later to trigger an event.) Note that these two voltages are both taken with respect to the circuit ground and that, for example, it may be the case that \$V_{HI}=V_{CC}\$ and \$V_{LO}=0\:\text{V}\$. But let's assume we don't need to know for sure, just yet, and allow these two voltages to be any two voltages with respect to ground but only where we require that \$V_{HI}\gt V_{LO}\$.

The two capacitors will charge up to their respective voltages, given enough time. Since \$V_{N_1}\approx V_{CC}\$ and \$V_{N_2}\approx 400\:\text{mV}\$. (I picked a middling value of \$400\:\text{mV}\$ because at some point the tiny current in \$D_2\$ entering the node will balance [equal] the tiny current leaving the node via \$R_8\$.)

Taking the bottom of these capacitors as their shared "reference" point, and assuming for now that this shared reference point sits at \$V_{HI}\$ just prior to a trigger event, the voltage across each will be \$\Delta V_{C_1}\approx V_{N_1}-V_{TRIG^-}= V_{CC}-V_{HI}\$ and \$\Delta V_{C_2}\approx V_{N_2}-V_{TRIG^-}=400\:\text{mV}-V_{HI}\$. Once charged, the circuit is stable.

Now, a trigger event occurs by causing \$V_{HI}\$ to go downward towards \$V_{LO}\$. The shared capacitor node is pulled hard down to \$V_{TRIG^+}=V_{LO}\$. This causes the other side of each capacitor to suddenly also be pulled down, too.


I wanted to keep things fairly abstract up to this point. But to avoid dealing with undue complexity now, it's time to decide that \$V_{HI}=V_{CC}\$ and \$V_{LO}=0\:\text{V}\$ and therefore that \$\Delta V_{TRIG}=V_{TRIG^-}-V_{TRIG^+}=V_{HI}-V_{LO}=V_{CC}\$.

The before and after voltages are:

$$\begin{align*}V_{N_1^-}&\approx V_{CC}&V_{N_1^+}&=V_{LO}+\Delta V_{C_1}= V_{CC}-\Delta V_{TRIG}=0\:\text{V}\\\\V_{N_2^-}&\approx 400\:\text{mV}&V_{N_2^+}&=V_{LO}+\Delta V_{C_2}= 400\:\text{mV}-\Delta V_{TRIG}=-\left(V_{CC}-400\:\text{mV}\right)\end{align*}$$

It's not too hard to see that \$D_1\$ will not be sufficiently biased to much affect the left stage. However, it's also now clear that now \$D_2\$ will be forward-biased. And very strongly so.

So \$D_2\$ now pulls hard-downward on the base of \$Q_2\$, turning \$Q_2\$ "off." This in turn allows \$R_4\$ now to pull upward on the base of \$Q_1\$ and turning \$Q_1\$ "on." \$D_1\$ will now oppose this a little for a moment, but it won't take long before \$C_1\$ changes its voltage enough that \$D_1\$ no longer drags much. (So there must be a certain width to the down-going pulse.)


That's about it. After the state change the roles are reversed and the above logic applies, but oppositely for the left and right stages.

The need for the two resistors occurs because while one of the stages might also have a diode through which its capacitor can charge the other one's diode can't serve that purpose. There needs to always be some DC path by which the capacitors can charge.

One thing that might arrive (and I think your question might also be asking) is that there will be a strong pull-down for one of the BJTs, during switching. This pull-down can possibly exceed the \$V_{BEO}\$ specification for the BJT, depending on your value for \$V_{CC}\$, causing it to zener. It might be useful to include a protection diode to cover that case when \$V_{CC}\gt V_{BEO}\$.


Postscript:

One of the better ways to try and understand a circuit that at first appears to be confusing is to redraw it. There are some rules you can follow that will help get a leg-up on learning that process. But there are also some added personal skills that gradually develop over time, too.

I first learned these rules in 1980, taking a Tektronix class that was offered only to its employees. This class was meant to teach electronics drafting to people who were not electronics engineers, but instead would be trained sufficiently to help draft schematics for their manuals.

The nice thing about the rules is that you don't have to be an expert to follow them. And that if you follow them, even blindly almost, that the resulting schematics really are easier to figure out.

The rules are:

  • Arrange the schematic so that conventional current appears to flow from the top towards the bottom of the schematic sheet. I like to imagine this as a kind of curtain (if you prefer a more static concept) or waterfall (if you prefer a more dynamic concept) of charges moving from the top edge down to the bottom edge. This is a kind of flow of energy that doesn't do any useful work by itself, but provides the environment for useful work to get done.
  • Arrange the schematic so that signals of interest flow from the left side of the schematic to the right side. Inputs will then generally be on the left, outputs generally will be on the right.
  • Do not "bus" power around. In short, if a lead of a component goes to ground or some other voltage rail, do not use a wire to connect it to other component leads that also go to the same rail/ground. Instead, simply show a node name like "Vcc" and stop. Busing power around on a schematic is almost guaranteed to make the schematic less understandable, not more. (There are times when professionals need to communicate something unique about a voltage rail bus to other professionals. So there are exceptions at times to this rule. But when trying to understand a confusing schematic, the situation isn't that one and such an argument "by professionals, to professionals" still fails here. So just don't do it.) This one takes a moment to grasp fully. There is a strong tendency to want to show all of the wires that are involved in soldering up a circuit. Resist that tendency. The idea here is that wires needed to make a circuit can be distracting. And while they may be needed to make the circuit work, they do NOT help you understand the circuit. In fact, they do the exact opposite. So remove such wires and just show connections to the rails and stop.
  • Try to organize the schematic around cohesion. It is almost always possible to "tease apart" a schematic so that there are knots of components that are tightly connected, each to another, separated then by only a few wires going to other knots. If you can find these, emphasize them by isolating the knots and focusing on drawing each one in some meaningful way, first. Don't even think about the whole schematic. Just focus on getting each cohesive section "looking right" by itself. Then add in the spare wiring or few components separating these "natural divisions" in the schematic. This will often tend to almost magically find distinct functions that are easier to understand, which then "communicate" with each other via relatively easier to understand connections between them.

The above rules aren't hard and fast. But if you struggle to follow them, you'll find that it does help a lot. (Even if you know almost nothing about electronics beforehand.)

Note that in the way I drew out the first schematic here, I teased apart what otherwise looked like a single, tightly connected circuit into two distinct sections (inverter stages) that were connect to each other via a very simple resistor.

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  • \$\begingroup\$ @beur_x Thanks for the kind comment. I might have written more and better, or less and better, but I didn't have the extra time. So I just hoped it was enough. \$\endgroup\$ – jonk Jan 19 '18 at 23:31
  • \$\begingroup\$ The simple yet powerful redrawing of the circuit really made it click, again thank you! \$\endgroup\$ – beur_x Jan 19 '18 at 23:34
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    \$\begingroup\$ @beur_x I very much recommend to everyone, when I think of it and get a chance, to attempt to redraw "confusing" circuits. It's often the fastest way to an understanding! \$\endgroup\$ – jonk Jan 19 '18 at 23:36
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The 220K and the 1nf set up a time constant. When one rc branch charges, the other discharges, because of the type of bias, this causes a one cycle condition of on and off. This is a basic Set-Reset flip flop. See the author's page (where that schematic originated) : http://www.electronics-tutorials.ws/waveforms/bistable.html and if you need more of a breakdown of the circuit (formulas, etc) you need to ask that as a different question.

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  • \$\begingroup\$ Also known as a toggle flip-flop. Because of DC cross feedback it cannot oscillate continuously. \$\endgroup\$ – user105652 Jan 19 '18 at 21:58

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