Strategy for Cortex M0 Peripheral Clock Speeds?

Question

I'm starting on learning the Cortex M, and coming from an 8 bit background.

I've got my demo board, blinking an LED and getting a working project out of STM32Cube.

I'm working my way through the system registers, but I'm a bit stymied on what to think about clock speeds for peripherals? This isn't really a consideration for any 8 bit firmware I've written.

For the ARM Cortex M0 architecture, what are the major considerations when you set clock speeds for APB1 peripherals?

Say I slow down my peripheral clock too much, what happens?

How could I go about calculating what speed I want for the peripherals?

Do the peripheral clock speeds account for much of the overall power consumption of the system?

Answer 1

Say I slow down my peripheral clock too much, what happens?

There will be delay accessing registers of those peripherals since you have to wait for the bus (AHB).

How could I go about calculating what speed I want for the peripherals?

Most of the time they just run full speed. Unless the energy budget requires otherwise.

Do the peripheral clock speeds account for much of the overall power consumption of the system?

That depends on the peripherals you have enabled. Some peripherals are hungry, some are not. This depends on their complexity.
The datasheet will have a table with the peripherals uA/MHz rating.
For example in the STM32F072:

Looking at these number might have you decide that, when you're only using a timer to output 100 Hz PWM to put that bus at 1 MHz instead of 48 MHz going to the core itself. And maybe not use TIM1 or TIM2.

However, this affects all peripherals on that bus. Including CAN or UART, and depending on the chip complexity the memories.

There isn't much to calculate. You will have sysclk from the PLL, and from then on there are only dividers. Find the clock tree in the reference manual, and play around with the clocks page in STMCubeMX.