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This question is further to my previous question: Alternatives to SPI because of EMI. I am toying with the idea of designing my own communication bus. I would be grateful if someone could cast their eye over my preliminary design, and tell me where I'm crazy...

I am currently using 2MHz SPI carried over 10cm long wires to seven ADCs on separate PCBs (shared CS, but each ADC has its own MISO line. It's bit-banged), but would like to replace it with something differential to reduce EMI. Problem is that there aren't many ADCs with a differential bus, so I am wondering if it's possible to design my own bus. At least the physical layer, and possibly the protocol too.

Design goals of the new bus:

  • use physically small components
  • low EMI
  • no more than 4 data wires (two pairs)
  • bandwidth of > 300kbps from each ADC. (>2.1mbps total)

Before you write me off as crazy for thinking about this, consider that it may not be so hard to do on a PSoC5. On that chip I can certainly design my own protocol in Verilog and have it implemented in hardware. And to some extent, I may be able to include the physical layer components too. What's more, I may be able to have seven of these things at the same time, all running in parallel in the master, one to each slave so that I can get good overall bandwidth.

And here is my preliminary idea:

enter image description here

It would be based on I2C, slightly modified to help it connect to the physical layer components. The SDA and SCL lines are now differential pairs. The SDA pair has the OR-ing property. This is achieved using one pin which can only drive high, and one which can only drive low. The SCL pair is driven exclusively by the master. The data rate would be turned up to at least 1mbps.

The master would be a PSoC5 with 7 master modules. The slaves would also be PSoC5s, with one slave module, and would use the integral ADC.

Thoughts:

  • Not too sure what's the best way to implement the pull up resistors and slew rate limiting components.
  • I assume I don't need any termination. If I limit the slew rate to about 80ns, it should be good for a 10cm long cable.
  • That is obviously not a proper differential transceiver. Am I wasting my time trying to make one out of gates?
  • Those Not gates cause some skew. It this likely to be a problem?
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  • \$\begingroup\$ Maybe LVDS is worth a look if you want differential signaling? \$\endgroup\$ – Saad Jul 5 '12 at 23:08
  • \$\begingroup\$ I don't think I've seen any I2C-style slave devices with separate SDA inputs and outputs. Also, if you're using a microprocessor-based I2C slave, you must allow slaves to hold SCK low in such a way that the master will be able to see it (the master will then hold off on sending the next bit until the slave releases SCK). Otherwise, if the master sends data without waiting for the slaves to be ready, things will fail badly. Alternatively, you could use SPI, and only use certain byte values for sending data (so every byte of "real" data would be transmitted as two bytes). If you do that... \$\endgroup\$ – supercat Nov 15 '12 at 18:11
  • \$\begingroup\$ ...since most SPI implementations will drop multiples of whole bytes in case of data overrun/underrun, you could have the master detect when the slave was unable to keep up and retransmit individual bytes until the slave was able to acknowledge them. \$\endgroup\$ – supercat Nov 15 '12 at 18:15
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Well, if you're going to have PSoC5's all around, I was recently reading about IEEE 1355. The DS-SE-02 signal link variant may do what you want. It calls for 4 signal lines: a data line and a strobe line in each direction. The only dedicated hardware I can find that implements 1355 is rad-hardened Spacewire gear, but this IEEE presentation claims that it can be implemented on an FPGA with 1/3 of the gates of a UART and operating at speeds 100 times faster than a UART.

A public copy of the full standard is available courtesy of CERN if you're up for a bit of light reading. I haven't had a chance to sit down with the full thing, so I can't speak for its EMI performance. Looking over the DS-SE section, it looks like you have to control for impedance in the transmission line and terminate at the receiving end.

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  • \$\begingroup\$ Thanks for this idea. It sounds interesting. Anything called Spacewire is fine by me. I'll take a look at it now... \$\endgroup\$ – Rocketmagnet Jul 6 '12 at 9:27
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Have you considered using RS485?

There are already many components designed to work on RS485 buses.

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  • \$\begingroup\$ Yes I have thought about it. It's certainly an option. I don't think they do OR-ing, but the master could transmit asynchronously on one pair, while the slaves take turns on the other pair. The only problem was that I couldn't find really small transceivers. Did I mention that I'm desperately tight on space. \$\endgroup\$ – Rocketmagnet Jul 5 '12 at 23:04
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    \$\begingroup\$ Is SOIC 8 too large for you requirements? I recently was considering using a Intersil ISL83485IBZ or a Texas Instruments SN65HVD11D transceiver on one of my projects. Both have SOIC 8 packages. \$\endgroup\$ – Bruno Ferreira Jul 5 '12 at 23:35
  • \$\begingroup\$ @Bruno - SOIC-8, are you kidding? :-) The PCB is 11 mm x 13 mm. \$\endgroup\$ – stevenvh Jul 6 '12 at 11:48
  • \$\begingroup\$ @stevenvh Did't notice the dimensions on the other question. I suppose a MSOP package doesn't solve your problem. If it does, maybe you could use ADM1485 \$\endgroup\$ – Bruno Ferreira Jul 6 '12 at 12:25

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