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I'm trying to get the timing report of STA. As I know, basically, there are 4 types of timing paths.

  1. Input to register

  2. Register to register

  3. Register to output

  4. Input to output

4 timing paths

Practically, I want to know what command do I need to get the 4 timing reports?

So far, I know how to make 2 paths:

report_timing -from [all_inputs] >report_from_all_input.txt

report_timing -to [all_outputs] > report_to_all_output.txt

but the other things not.

Would you help me how to get the timing report of 4 paths in Design Compiler?

update

I come across the below message when I run with below command.

report_timing -from [all_inputs]    -to [all_registers]  > report_input2reg.txt
report_timing -from [all_registers] -to [all_registers]  > report_reg2reg.txt
report_timing -from [all_registers] -to [all_outputs]    > report_reg2output.txt
report_timing -from [all_inputs]    -to [all_outputs]    > report_intput2output.txt

-output

Warning: cell 'u_phase_sub17/p_reg[6]' is of the wrong type. (UID-119)
Warning: cell 'u_phase_sub17/p_reg[8]' is of the wrong type. (UID-119)
Warning: cell 'u_phase_sub17/p_reg[9]' is of the wrong type. (UID-119)
Warning: cell 'u_phase_sub17/p_reg[10]' is of the wrong type. (UID-119)
Warning: cell 'u_phase_sub17/p_reg[11]' is of the wrong type. (UID-119)
Warning: cell 'u_phase_sub17/p_reg[12]' is of the wrong type. (UID-119)
Warning: cell 'u_phase_sub17/p_reg[13]' is of the wrong type. (UID-119)
Warning: cell 'u_phase_sub8/p_reg[3]' is of the wrong type. (UID-119)
Warning: cell 'u_phase_sub8/p_reg[4]' is of the wrong type. (UID-119)
Warning: cell 'u_phase_sub8/p_reg[7]' is of the wrong type. (UID-119)
Warning: ...13357 additional objects are of the wrong type. (UID-119)
Warning: Ignoring all 13367 objects in collection '_sel29' because they are not of type pin, port, net, clock, or ge
Error: Value for list '-from' must have 1 elements. (CMD-036)
0

Did I use that commands correctly? I only expected it to make bunch of the below timing lists.

  Startpoint: i_f0[2] (input port clocked by clk)
  Endpoint: trad_28_reg[68]
            (rising edge-triggered flip-flop clocked by clk)
  Path Group: clk
  Path Type: max


  Point                                    Incr       Path
  -----------------------------------------------------------
  clock clk (rise edge)                    0.00       0.00
  clock network delay (ideal)              0.00       0.00
  input external delay                     0.10       0.10 f
  data arrival time                                   7.41 
  ...
  clock clk (rise edge)                    7.80       7.80
  clock network delay (ideal)              0.00       7.80
  clock uncertainty                       -0.05       7.75
  library setup time                      -0.05       7.70
  data required time                                  7.70
  -----------------------------------------------------------
  data required time                                  7.70
  data arrival time                                  -7.41
  -----------------------------------------------------------
  slack (MET)                                         0.29
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  • \$\begingroup\$ I tried myself. It seems that Design Compiler requires -data_pins switch, however PrimeTime does not. I updated the answer accordingly. \$\endgroup\$ – ahmedus Jan 22 '18 at 13:01
  • \$\begingroup\$ @ahmedus Thanks I think it works. and mostly from reg to output path have no path report. \$\endgroup\$ – start01 Jan 23 '18 at 2:24
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The all_registers command can be used to get a collection of sequential cells. The basic use of it is not different from all_inputs and all_outputs commands.

The 4 timing reports may be generated as follows.

  1. report_timing -from [all_inputs] -to [all_registers -data_pins]
  2. report_timing -from [all_registers -data_pins] -to [all_registers -data_pins]
  3. report_timing -from [all_registers -data_pins] -to [all_outputs]
  4. report_timing -from [all_inputs] -to [all_outputs]

Note: PrimeTime supports that command as well as Design Compiler, but -data_pins (or -clock_pins) switch is mandatory for Design Compiler only.

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