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I need a controllable frequency for use in a radio transceiver with a range of 3–50MHz (i.e., 80m–6m). The frequency needs to be selectable using a microcontroller. Because chips like the Si5351 tend to give birdies, I want to use a DDS. However, that would mean a >100MHz crystal oscillator since as far as I know all DDS chips require an at least twice faster input signal. It's not so easy to get a >100MHz crystal oscillator, and I want to use common parts as much as possible.

Would it be feasible to use a lower frequency crystal oscillator and a PLL to scale it up? Specifically, I'm thinking about the ADF4002 PLL with the AD9913 DDS. Or are there other options that I'm missing?

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  • \$\begingroup\$ Also to be considered is that when multiplying up any initial frequency offsets or drifting will be increased by the same multiple. When dividing down initial offsets and drifting will be divided down. \$\endgroup\$ – Nedd Jan 22 '18 at 10:32
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    \$\begingroup\$ If you can find a 50MHz oscillator there are very easy ways to double its output - such as an XOR gate and an R-C delay into one input - clean that up with a 100MHz tuned circuit and you have a stable 100MHz clock. \$\endgroup\$ – Brian Drummond Jan 22 '18 at 12:25
  • \$\begingroup\$ IMO a transceiver is made with bunch of frequency mixers, PLLs, filters. I don't know the new approach of using DDS in radio, but maybe you have underestimated all analogue part and now the only problem is the DDS. A schematic block would help to understand all stages/mixers of your transceiver. \$\endgroup\$ – Marko Buršič Jan 22 '18 at 13:45
  • \$\begingroup\$ @MarkoBuršič it's not that new as far as I can tell. I'm inspired by the 2007 ATS3b by Steve Weber, KD1JV. The manual is here, the relevant schematics are on pp. 28–29. This one uses a 60MHz oscillator and a DDS, but no PLL, meaning the maximum frequency is 30MHz, so it supports the 10m band, but not 6m. The reason why I want to use a DDS and not a traditional VCO is that I want to be able to set the frequency with a microcontroller. \$\endgroup\$ – user17592 Jan 22 '18 at 14:02
  • \$\begingroup\$ @BrianDrummond interesting idea, I will experiment with that. Perhaps you could consider adding it as an answer. \$\endgroup\$ – user17592 Jan 22 '18 at 14:02
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If you can find a 50MHz oscillator there are very easy ways to double its output - such as an XOR gate and an R-C delay into one input - clean that up with a 100MHz tuned circuit and you have a stable 100MHz clock.

schematic

simulate this circuit – Schematic created using CircuitLab

The output mark-space ratio is dependent on logic switching levels and RC : here I've set the "half life" of an R-C filtered edge to 5 ns (50% of a 100MHz cycle) - t(1/2) = 0.693*RC) so RC = 7 ns. You may have to adjust to account for source impedance, parasitic capacitance, board trace length etc.

I suggest an L-C filter to clean it up, followed by a buffer to square it if necessary. This should reduce jitter if the input mark-space ratio is not 50% - it'll also improve the mark space ratio due to R-C errors.

It was well known long before Peter Alfke's classic Xilinx white paper "Six easy pieces" which includes a variant, (No.4) using a flipflop and an inverter to provide the delay - cleaner than an R-C or delay line inside an FPGA.

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Have you considered just using frequency multiplying circuits? a PLL is oftcourse another option but that requires more components and you need to be sure your loop is stable etc. And if you have a bad loop/VCO it could very well be you still have suprious tones or more phase noise than just going with a integer multiplying method.

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  • \$\begingroup\$ Thanks for the quick response. Perhaps I'm using the term 'PLL' incorrectly. The ADF4002 is listed as an 'Integer-N PLL' - is that not what you mean by 'integer multiplying method'? If not, how would I find a chip using the integer multiplying method? \$\endgroup\$ – user17592 Jan 22 '18 at 10:20
  • \$\begingroup\$ A PLL is a more complicated system. There exist devices that can just double/triple/etc frequency of an input signal, usually by using some form of non-linear behaviour. A PLL is a system that controls the frequency of a entirely seperate oscilator (which is usually the output) and then compares that frequency (or that frequency devided by a certain amount to an input reference frequency. This way you have a feedback loop. They can give you much more control over the output and higher performance but are much trickier to get right. \$\endgroup\$ – Joren Vaes Jan 22 '18 at 10:28
  • \$\begingroup\$ In addition, the ADF4002 that you suggests still requires an external VCO in order to operate. \$\endgroup\$ – Joren Vaes Jan 22 '18 at 10:29
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    \$\begingroup\$ He may have meant the well known tripler, which puts a spiky waveform (lots of third harmonic) into an L-C filter (tuned to the third harmonic). As your spectrum broadly overlaps the classic amateur radio spectrum, you'd find a bookful of interesting ideas here ... amateurradiosales.co.uk/product-page/… \$\endgroup\$ – Brian Drummond Jan 22 '18 at 14:55
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    \$\begingroup\$ The Analog Devices Multipliers you list @Keelan are outside of your scope (I think none of them even goes down to the frequency you want). Commonly used tricks for tripling is indeed using the third harmonic of a waveform. For doubling you can use a simple diode (rectification) and get the second harmonic from that. \$\endgroup\$ – Joren Vaes Jan 23 '18 at 7:16
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Would it be feasible to use a lower frequency crystal oscillator and a PLL to scale it up?

I've built a PLL from the ADF4111 (very similar to the ADF4002) that generated 400 MHz using a common-collector colpitts oscillator with a varicap for VCO tuning and it worked great. I used a small PIC to upload the register values and it, well... it just worked first time. My reference clock was 10 MHz.

The circuit was part of an FM modulator for a data transmission system (10 Mbps) and data was attenuated and AC coupled onto the varicap tuning pin.

Or are there other options that I'm missing?

Maybe there are some DDS chips that already have an in buit PLL?

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Your options also depend on the spurious response, hence the non-random noise floor you will experience. DDS have spurious outputs, as well as phase noise caused by all the circuitry touching the zero-crossing points of the DDS internal clocking/dividing activities.

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