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I'm working with convolutional neural networks and I have written a code to make the convolution of two 3x3 matrices. This is my code: https://www.edaplayground.com/x/6G7h Now I want to make the convolution of two matrices: 400x400 and 3x3. That is 160,000 elements x 9 elements, I think that's a lot.

So I would like to ask you guys, what's the most optimized way to do this?

Thanks in advance.

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    \$\begingroup\$ Have you synthesized that code into an FPGA? If so what FPGA, what was the utilization and what speed did you get? I am also missing code on how you are going to supply the inputs values and read out the results. \$\endgroup\$ – Oldfart Jan 22 '18 at 11:59
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    \$\begingroup\$ Looking to your "design" file sounds like you treat hardware as being a software-like. Without understanding how hardware works and what Verilog source is translated to you would hardly be able to optimize. Most probably you will have ti use embedded RAM for the operation. \$\endgroup\$ – Anonymous Jan 22 '18 at 12:04
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    \$\begingroup\$ This question will be useless when that cloud-whatever website goes down next year. Please make sure that everything necessary to answer the question is included in the question. \$\endgroup\$ – pipe Jan 22 '18 at 12:19
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    \$\begingroup\$ Don't forget that you can chop matrices up into blocks and multiply block by block. In other words, reuse multipliers at the cost of lower operation frequency. \$\endgroup\$ – Harry Svensson Jan 22 '18 at 12:19
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    \$\begingroup\$ Impossible to answer without knowing what you want to optimise for. And if you can't be bothered to tell us, we can't be bothered to guess. \$\endgroup\$ – Brian Drummond Jan 22 '18 at 12:41
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This looks like a case of premature optimization. Start by implementing your algorithm iteratively, and see how fast it performs. Then you'll know exactly how much faster you need to make it, and decide how much operations (and which ones) you will do in parallel.

Implementing the whole thing as a 1-step combinatorial function will not work well: it will require a ton of resources and won't even run that fast without proper pipelining.

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You're jumping the gun assuming an FPGA for this problem (http://parallelpoints.com/why-use-an-fpga/)

Describe in much more detail what you want to achieve... data sizes, rates, latency requirements. You have to prove to yourself that you have a significant problem. Only then you can think about potential specific solutions (of which FPGA is likely to be the penultimate item on your list before "full-custom ASIC" :)

Then, things like: do the input data arrive in sequence or are they already in memory? Where is that memory - how are you going to transfer it to your accelerator?

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