Why is having a 2 stage flip-flop desirable? Are there advantages of having a master-slave compared to a one stage JK flip flop?
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\$\begingroup\$ Have you tried google for expert answers. If not, why not? \$\endgroup\$– Andy akaJan 22, 2018 at 14:31
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1\$\begingroup\$ Essentially, much cleaner waveforms and timings. I'll let the answers explain how. \$\endgroup\$– user_1818839Jan 22, 2018 at 14:58
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2\$\begingroup\$ There isn't really such thing as a one stage JK flip flop (at least in common implementations), with one stage you only get a latch. \$\endgroup\$– mbrigJan 22, 2018 at 18:45
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\$\begingroup\$ @mbrig: I can't think of any advantage of a single-stage JK "thingy" over an RS latch with enable. \$\endgroup\$– supercatJan 22, 2018 at 18:51
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1\$\begingroup\$ @mbrig: I'd call that circuit an edge-triggered dynamic register. While the terms "register" and "flip flop" are often used interchangeably, I'd be disinclined to use the latter term for any kind of register that wasn't fully static during at least one clock phase (most registers are fully static at all times). By contrast, the dynamic latch relies upon the fact that the first phase will set the input to the second stage low whenever the D is high, high whenever D input and clock are both low, and let it float (holding its state for a few microseconds or maybe milliseconds) otherwise. \$\endgroup\$– supercatJan 22, 2018 at 19:56
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3 Answers
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The problem with simple JK latch is the race condition.
Race condition is that as long as the clock is high, when the propagation delay is less than the pulse period, the output toggles between 0 and 1 if J=K=1.
This is undesirable because the value can be undetermined. Master-Slave configuration of two JK latches eliminates this race problem.
A simple positive edge triggered Master-Slave JK flip-flop consists of two cascaded latches: One negative latch and a positive latch.
Latches are level triggered. When the clock is low, The first latch is in transparent mode the second latch is in hold mode. When the clock is high, The first latch is in hold mode the second latch is in transparent mode. They together act as a positive edge triggered Master-Slave JK flip-flop.
When clock makes transition from 0 --> 1, the first latch moves from transparent to hold mode, while the second latch moves from hold to transparent mode at the same time. i.e., The output of the first latch just before that rising clock moment would be the data sampled by the second latch. This data is available at Q after clock becomes high, because the second latch is now in transparent mode. Once the clock becomes high, changes in the input of the first latch is not reflected anymore at the output Q because it is in hold mode now. In the previous case, when clock is high and J=K=1 , the outputs goes on toggling till the clock goes low. This problem no longer exists in this case.
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\$\begingroup\$ If the signals applied at J and K(to change the state of the flip flop) in above diagram are longer than propagation delay of latch-1, then output of latch-2 will become indeterminate in case J=K=1. Otherwise it will be determinate and the outputs will toggle in case J=K=1. \$\endgroup\$ Mar 1, 2020 at 16:03
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Master slave flip flops of any variety are usually a combination of a positive level controlled flop with a negative level controlled flop.
When combined properly this gives you an edge controlled flop.
It is easier to design sequential logic which is controlled by one edge rather than two levels. You have to design the clocks of level designed logic to be non overlapping so that you do not violate setup and hold times of the level triggered flops and that the outputs change when you want them too. In the past logic design has been done this way particularly in IC design. It is much easier to just deal with one transition and have much of the translation to two level design and timing taken care of for you in the design of the edge triggered flops.
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Well the main advantage for using a master-slave instead of a JK for toggling is the master-slave doesn't allow the output to change when q changes and waits for a clock pulse. This prevents false triggering that is referred to as "race". This is a pretty good article about flip-flops: https://www.electronics-tutorials.ws/sequential/seq_2.html
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\$\begingroup\$ Isn't this a property of all edge triggered flip-flops? \$\endgroup\$– beur_xJan 22, 2018 at 15:41
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1\$\begingroup\$ the extra jk in the master slave ensures reliable toggle action with the clock by adding another flip flop and forcing a wait state at the slave. This ensures clean timing. \$\endgroup\$– drtechnoJan 22, 2018 at 16:27