If a flip-flop D is given in input D = 1 when the clock is C = 1, and then, when the clock becomes C = 0, D = 0, what will be the status eventually assumed by the flip-flop? Will it be 0?

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    \$\begingroup\$ That really depends on the timing of those events. \$\endgroup\$ – Trevor_G Jan 23 '18 at 20:53
  • \$\begingroup\$ Depends on the specified clock edge the FF operates on, and the specified setup and hold times. If it's rising edge triggered the FF will not change state from the clock falling edge. \$\endgroup\$ – Spehro Pefhany Jan 23 '18 at 21:11

For DFF to function as described in the datasheet, there're specific timing requirements must be met. Refer to the 7474 DFF datasheet, in particular page 6. It defines the following requirements:

  • tw, pulse duration. This is minimal duration of the respective signal in specific state (high or low);
  • tsu, data input setup time before CLK transitions from low to high;
  • th, hold time. Data input must remain in its state after CLK transitions high for the declared amount of time.

If your circuit using DFF complies with these requirements, declared functionality is guaranteed by the manufacturer.

However if something gets out of these requirements (out of specification), then behavior of the DFF - its state and level of its output signals - are not guaranteed, most probably causing malfunction of the whole device.

Next, about output levels. The same datasheet I linked to above shows Function table on its first page. It identifies the states and outputs of the DFF given specific input conditions. You must find answer for any scenario in this table.

  • \$\begingroup\$ What data-sheet... \$\endgroup\$ – Trevor_G Jan 24 '18 at 20:19

This question is really unanswerable as is.

D-Types come in various flavours... Unfortunately people are often bad at using the complete name for which version they are talking about.

A D-Type Flip-Flip can be the simple...

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to the more complex Edge Triggered D-Type Flip-Fop like the 74xx74 device.

enter image description here

In the simple case the clock line more acts as an enable than an actual clock. As you should be able to see, when the clock line is high the Data line is passed through to the S-R latch and changing it while clock is high will change the outputs. In my opinion, the circuit is actually more of a transparent latch.

In the more complex edge triggered device, the extra flip-flops prevent this and the output latch is only set on the rising edge (in this case) of the clock.

For both circuits the final state depends on the timing of the data and clock edges. In some cases the output can actually oscillate due to metastability. The other answers here have covered those requirements in detail so I will not expand on that further here other than to say changing C and D at the same time is a bad idea and will produce unpredictable results.


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