I have to write a code for frequency divider from 161.24MHz to 8KHz in Verilog. Please help to write a code.


closed as unclear what you're asking by Dave Tweed Jan 24 '18 at 12:50

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    \$\begingroup\$ Welcome to the site. Please quickly realise that this is not a free design house, homework-answering service or an on-line technical encyclopedia, copied out to you on demand. People will help you take the next step if your question shows that you've done as much as you possibly could on your own - which your post doesn't, I'm afraid. Please revise your question showing your work and findings so far, in considerable detail. Or delete the question if Internet searches give you your answer anyway. Again, a warm welcome to the site. \$\endgroup\$ – TonyM Jan 24 '18 at 7:34
  • \$\begingroup\$ "Please help to write a code.", that's something you can say to someone you're paying. \$\endgroup\$ – Harry Svensson Jan 24 '18 at 7:44
  • \$\begingroup\$ "I have to write a code" - so why are you asking us to write it for you. I'm guessing this is a homework exercise. \$\endgroup\$ – Tom Carpenter Jan 24 '18 at 9:48
  • \$\begingroup\$ Welcome to EE.SE! This appears to be a homework question. As such, you need to show us your work so far, and explain which part of the question you're having trouble with. For future reference: Homework questions on EE.SE enjoy/suffer a special treatment. We don't provide complete answers, we only provide hints or Socratic questions, and only when you have demonstrated sufficient effort of your own. Otherwise, we would be doing you a disservice, and getting swamped by homework questions at the same time. See also here. \$\endgroup\$ – Dave Tweed Jan 24 '18 at 12:51
  • \$\begingroup\$ Why dont you use google.com.... #facepalm \$\endgroup\$ – Mitu Raj Jan 24 '18 at 14:24

161.24 / .008 = 20155 . So you can simply build a 15 bit counter that counts up to 20154 and generate your output based on that. If you just need single cycle pulses, then generate a pulse when the counter overflows. If you need a 50% duty cycle, then use a comparator to generate a high level when the counter is in one half of its range.

  • \$\begingroup\$ Thank you for the reply, can you please explain with the Verilog code. \$\endgroup\$ – SAURAV Jan 24 '18 at 9:10
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    \$\begingroup\$ If you don't know how to write a counter in Verilog, then you're not prepared for this assignment, regardless of whether it's homework or professional. \$\endgroup\$ – Dave Tweed Jan 24 '18 at 12:50

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