I have to write a code for frequency divider from 161.24MHz to 8KHz in Verilog. Please help to write a code.
closed as unclear what you're asking by Dave Tweed♦ Jan 24 '18 at 12:50
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161.24 / .008 = 20155 . So you can simply build a 15 bit counter that counts up to 20154 and generate your output based on that. If you just need single cycle pulses, then generate a pulse when the counter overflows. If you need a 50% duty cycle, then use a comparator to generate a high level when the counter is in one half of its range.