I am looking for an efficient (in terms of footprint) way to periodically collect data from a multitude of processing elements (PEs) within an Spartan6-based design.
I currently have 16 PEs, but when the design scales up it may become up to 64. Each PE outputs two 16-bit words of data (
B) at a frequency of ~100 KHz. The output data from all PEs needs to be collected and added to two sums (
B_sum). The system clock will be >100 MHz, so I have >1000 clock cycles to collect the data from the PEs.
The easiest way to do it would be two 16-bit wide multiplexers (
B_mux) with one input per PE each. For 16 PEs, this would cost 128 slices plus 512 interconnect lines within the chip, and it would take 16 clock cycles to collect the data. Since it doesn't need to be that fast, I am wondering if there is a more resource-efficient way to do it.
I was thinking of serializing the data in some way. This would save interconnect lines, but I would use more slices to implement the serializers in every PE. I would also need shift registers with parallel outputs (hence no SRL32) for de-serialization.
Some of you suggested I may have answered my own question. Serialization obviously comes to mind, however I am not sure whether it is really going to be more efficient. My question is not so much whether serialization is feasible, but I am concerned that serializers for every PE will use up more FPGA resources than a 16-bit multiplexer with inputs for every PE. Maybe there is some clever implementation I haven't thought about, but it seems to me that the fat mux is really the most resource-efficient way. Am I wrong?