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I'm in dire need of compile-time generated constant memory of ~512K x 16Bit on the Spartan 3 Starter Kit Board. I'm configuring the board over the JTAG port, and wondered if

a) there is a way to pre-configure data into the on-board SRAM, to read it on runtime

b) there is a good way to implement ROM (the way I tried exceeds the Boards capabilities at 8k x 16Bit)

c) there is some other good advice on the matter / things I have not considered?

I'm using the Xilinx ISE, VHDL.

thanks in advance.

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2 Answers 2

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a) You can't get ISE to automatically preconfigure your onboard SRAM - but you can of course manually make your design initialize it at startup (although this will require the data to be present somewhere else in the system, which basically defeats the purpose).

b) Create a blockram, and assign a .coe file with the desired contents to it, or use initialization attributes to describe the contents. You can read more about this for instance in Chapter 4 of the Spartan 3 user guide (UG331). Of course, with your size of ROM, that's going to be a bit difficult.

c) Other ideas could be to use a SPI FLASH chip (or similar), implement a small serial receiver design in the FPGA, and then load your FLASH chip contents from for instance HyperTerminal. Since it's a FLASH chip, you'll only have to do this once, and once it's done, you can remove the serial receiver design, and load your final design instead.

SPI FLASHes are quite cheap and easy to work with, but it also depends on how fast you need to access the contents. As it's serial, you wont be getting your datawords at 50MHz for instance (as that'd require your SPI interface to run at at least 800 MHz, which I'm reluctant to think is possible in a Spartan3). Parallel FLASH chips are out there also, but I'll admit that I don't have much experience with those.

An example of a SPI FLASH could be one of Atmels Dataflash chips.

In many cases you can also use the FLASH device that you store the FPGA bitstream in to store extra user data. Have a look at XAPP694 to see an example of how this is done.

The retro-way of doing this is to use a dual-inline EEPROM (or similar) and an EEPROM burner. Program the chip from your computer, and then mount it in your design.

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    \$\begingroup\$ I forget if it is possible on that particular board or not, but sometimes if the flash device for storing the FPGA bitstream is overlarge, you can have your design read additional data out of it and copy that to the external ram, much as with the spi flash idea. \$\endgroup\$ Jul 8, 2012 at 3:37
  • \$\begingroup\$ Of course, almost forgot about that. I've added a link to a relevant application note. \$\endgroup\$
    – sonicwave
    Jul 8, 2012 at 12:38
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There are many ways to create ROM's inside of an FPGA using VHDL. But honestly it is borderline too big to really put into an answer here. Without cutting down your question into something more manageable it will be difficult to give a complete answer.

But, let me start by giving you an idea about what kinds of things are possible (a.k.a. what I've done with Xilinx ISE)...

At compile time your VHDL code can read a text file that has the binary representation of the contents of your ROM. Each line of the text file would have something like "001011101" that represents the contents of that word of the ROM (or initialized RAM). Note: The last time I tried this, which was several versions of ISE ago, you were limited to binary "text". I know that other VHDL synthesis tools might support something more complex and useful.

At compile time you can calculate the contents of ROM (or initialized RAM). In one project of mine, I populate the ROM with a compile-time-calculated sine wave table. In a different project I calculate the coefficients for a filter and store that in the ROM. I should emphasize that the contents of the ROM are calculated at compile time, not simply read from another file or other canned source of data. In this way the data will change to reflect anything relevant, like the bit depth of the sine wave table or the number of taps of the filter. I can even do my calculations in floating point and then convert it to std_logic_vector before putting them in the ROM.

In my VHDL code I can specify in a nice way what the ROM contents should be. Essentially listing out what the contents similar to this: rom_contents := ("01001", "10111", "00111", ..); You can even use VHDL functions to convert non-std_logic_vector data into std_logic_vectors, making your VHDL code more readable or easy to maintain.

There are several key things to knowing how to do this:

The primary key is to simply know VHDL inside and out. Know how it's data types work and how to manipulate them. There is nothing Xilinx specific here, as these things are FPGA manufacturer independent (although not all VHDL sythesis tools support all kinds of VHDL constructs).

The next key is to look at example code. Simply going to the Xilinx web site and search for "ROM Coding techniques" will return lots of information. Even the Xilinx XST documentation has lots of info in there. Most of that info is in the 10+ megabyte XST users guide PDF, so know that in advance before trying to open that gigantic file.

If you gave me something specific I could dig up some example code. And by specific, I need to know exactly what you mean by "compile-time generated constant memory". There is no way I can give you more generic examples of ROMs, that would just be too much. But a very specific example is possible.

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  • \$\begingroup\$ Thanks for the Answer! But you kind of missed the Question. Thing is, there is no ROM on the board. At all. And my attempts at creating sufficient ROM via vhdl code have ended in dead-ends. Question was, if I could somehow pre-initialize the on-board SRAM via the JTAG port. \$\endgroup\$ Jul 6, 2012 at 14:36
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    \$\begingroup\$ @AndreasHenning Ah, um, "shoot". I read your ROM size as 512x16, not 512Kx16. In FPGA's you can create ROMs inside the FPGA, but not ROM's of that size in that FPGA. You're only option is to add some kind of Flash EPROM chip to the board and then program it separately from the FPGA-- so it would not be a "compile time generated" ROM. It is not possible to do this entirely inside the FPGA. \$\endgroup\$
    – user3624
    Jul 6, 2012 at 14:41
  • \$\begingroup\$ well, duh :( But it's good to have a definite Answer. Thanks a lot! \$\endgroup\$ Jul 6, 2012 at 14:43
  • \$\begingroup\$ by the way, if you're wondering why your answer is not yet accepted, I am still waiting for an Answer to parts a) and c) :) \$\endgroup\$ Jul 7, 2012 at 6:42
  • \$\begingroup\$ @andreashenning if your wondering why I haven't answered a) and c) it's because you need to be more specific in your requests. At the moment the only advice I can give is "learn everything about VHDL" but that is as vague as your questions. \$\endgroup\$
    – user3624
    Jul 7, 2012 at 17:43

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