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This is page 16 from But How Do It Know?:

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I don't understand this part:

If 'i' and '0' were on before's' got turned off, gate 3 had both inputs off, and gate 4 had both inputs on. When 's' goes off, 'a' comes on, which is one input to gate 3. But the other input is off, so nothing changes, '0' stays on. If 'i' and '0' were off before's' got turned off, gate 3 had both inputs on, and gate 4 had both inputs off. When 's' goes off, 'b' comes on, which is one input to gate 4. But the other input is off, so nothing changes, 'c' stays on and '0' stays off.

((But the other input is off)) It was off not "is" off !!

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I'd use a different description here. I find the description you included to be overly technical without any attempt to allow the reader to see the bigger picture.

schematic

simulate this circuit – Schematic created using CircuitLab

Let's look at a table for the blue dashed region above:

$$\begin{array}{cc|cc} \text{A} & \text{B} & \text{C} & \text{OUT}\\ \hline 0 & 0 & 1 & 1 & \text{Not used}\\ 0 & 1 & 0 & 1 & \text{STATE=1}\\ 1 & 0 & 1 & 0 & \text{STATE=0}\\ 1 & 1 & hold & hold & \text{KEEP}\\ \end{array}$$

Note that in the above table, one of the cases isn't used. You will see that fact in the table below, which shows the values of \$A\$ and \$B\$ that can be generated by combinations of \$IN\$ and \$S\$ (namely, the green dashed region above):

$$\begin{array}{cc|cc} \text{IN} & \text{S} & \text{A} & \text{B}\\ \hline 0 & 0 & 1 & 1 & \text{KEEP}\\ 0 & 1 & 1 & 0 & \text{STATE=0}\\ 1 & 0 & 1 & 1 & \text{KEEP}\\ 1 & 1 & 0 & 1 & \text{STATE=1} \end{array}$$

(You can see that the unused state I mentioned for the blue dashed region above doesn't occur, at all. So you don't need to worry about it.)


Okay. That's using tables to help get across some details.

Now, let's just use our brain.

When \$S=1\$, whatever is at \$IN\$ will appear inverted at \$A\$. In this case, \$A=\overline{IN}\$. Also, since \$A\$ is the input to the NAND gate for \$B\$, whatever is at \$A\$ will also be inverted at \$B\$. So it follows then that \$B=\overline{A}=IN\$. That's when \$S=1\$.

Why? Because when \$S=1\$ it basically converts the first two NAND gates into inverters, which invert their input to generate their output. You can look at \$S\$ being an inverter enable line. When \$S=1\$ then the first two NAND gates are enabled to invert their inputs.

As a consequence, when \$S=1\$ then \$A=\overline{IN}\$ and \$B=IN\$.

When \$S=0\$, you can see that it doesn't matter what \$IN\$ is, the result is always the \$KEEP\$ state. So when \$S=0\$, whatever was present at \$OUT\$ is kept.

When \$S=0\$, it disables the first two NAND gates so that they ignore their inputs and simply drive their outputs to HIGH.

As a consequence, when \$S=0\$ then \$A=1\$ and \$B=1\$.


Hopefully, those two approaches provide enough to help.

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  • \$\begingroup\$ I understand all this but again the same confusing part: why does "hold state" lead to keep state?? what I am thinking of is that the faster wire well pass first, Back to the first table suppose "A" wire is faster and there will be no electricity in wire "C" so this will lead to some output which will determine the new value of wire "C" which will make new output and so on ! \$\endgroup\$ – user175786 Jan 24 '18 at 21:16
  • \$\begingroup\$ @NourA.Hakim Take the information I provided above and, using your own approach, apply any arbitrary delay you want to each gate. Also, set up a timing diagram with an arbitrary phase relationship for \$IN\$ and \$S\$. Then work through the details. You will only understand once you actually spend the time, yourself. It's not hard to do. It's just boring work that is better done by you than me. This is something I think you need to actually sit down and work for. I've provided you the overview framework for you to get your own answer and one you will understand better if you do it. \$\endgroup\$ – jonk Jan 24 '18 at 21:26
  • \$\begingroup\$ The gates are NANDs. Their output is 1 IFF both inputs are 0. When A & B are both 1, then the NANDs act as NOT gates. Thus they will stick in their current state. When the gates are first powered up, they will settle in one state, in a non-deterministic manner. \$\endgroup\$ – CSM Jan 24 '18 at 21:27
  • \$\begingroup\$ @NourA.Hakim One more thing. I'm very much confused by your phrase, "there will be no electricity in wire ..." There is always something there. It may be a 0. It may be a 1. It may also be an indeterminate state that cannot be said to be either of them and where the logic gate design itself would need to be consulted or else a random guess made, if the model is inadequate. But the idea of "no electricity" just makes no sense to me. I've no idea what you are thinking, in writing that. \$\endgroup\$ – jonk Jan 24 '18 at 21:32
  • \$\begingroup\$ @NourA.Hakim A "0" is just a human concept. We choose to assign certain qualities in nature to our idea of 0 and 1, perhaps. But nature knows nothing itself about that. So while 0 might mean nothing to you, your mental conception of 0 is meaningless to a universe that has no human conception. \$\endgroup\$ – jonk Jan 24 '18 at 23:39
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I'm not even going to try to read and parse that lengthy description.

Divide the circuit into two parts.

The first part is gates 1 and 2. It should be clear that if S ("strobe") is low, then both gates must be high. When S goes high, only one gate or the other will go low.

The second part is gates 3 and 4, which form a simple R-S flip-flop. The output of gate 1 is the "set" input (active-low), and the output of gate 2 is the "reset" input (also active-low). As long as both inputs are high, the mutual feedback between these two gates will cause them to retain whatever state they were last in.

Therefore, if I ("input") is high when S is pulsed high, gate 1 will pulse low and "set" the flip-flop. Similarly, if I is low when S is pulsed high, gate 2 will pulse low and "reset" the flip-flop. As long as S is low, I cannot affect the output.

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  • \$\begingroup\$ Whenever a and b are both high, the only thing that determines the output state (O and C) is the feedback between them. If O is high, then C must be low, which insures that O remains high. Similarly, if C is high, then O must be low, which insures that C remains high. The only thing that can perturb this positive feedback is driving either a or b low, which is the function of gates 1 and 2. \$\endgroup\$ – Dave Tweed Jan 24 '18 at 21:35

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