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I would like to add a sink only Type C port to my project (non-PD power only, no data) but would like to include 6 lines for debug purposes (SWDIO, SWDCLK, UART lines, and nRST).

I was wondering what lines would be safe to use for this (if any)? Could I use the Tx +/- (top and bottom, 4 pins total) lines plus the SBU lines? It doesn't have to be symmetrical for me, I can mark my debug cable.

That also brings up another question, if I plug an A to C cable into my computer, will using the SS Tx lines for SWD on my UFP result in any enumeration error for USB? Reading USB 3.x SS enumeration, it sounded like the Host would first poll the Rx lines for a RC time sink, if nothing is found, move on to USB2.0. What happens to the peripheral Tx lines if USB3.0 enumeration fails?

Thanks!

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  • \$\begingroup\$ I also don't need to pass USB spec. It is a USB type C purely for ID. \$\endgroup\$ – Josh Jan 25 '18 at 0:33
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Instead of inventing your own debug connections over Type-C connector, I would advise to align your project with Type-C Standard, "Debug Accessory Mode", see Appendix B of Type-C Specifications. But if you want to use Type-C and mark it as proprietary debug port, you can do whatever you want with connections, provided that you use GND and VBUS pins properly. Accidental connect to live USB port will do no harm other than "fail to connect/enumerate" message. The error will come and go, why be concerned?

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  • \$\begingroup\$ Thanks Ali, I am converting over from an existing micro-USB design and just using the plug with no PD capabilities so I can't enter Accessory mode. If I connect VBUS and ground and say it is a proprietary debug port, do I need to also pull CC lines to GND with a 5.1kohm resistor for charging purposes? \$\endgroup\$ – Josh Jan 25 '18 at 17:25
  • \$\begingroup\$ @Josh, if you want any regular Type-C port to supply power to your device, then yes, you must use CC lines with 5.1k pull-downs, to inform the port that you are a device with sink. Otherwise the regular Type-C port won't supply any VBUS. \$\endgroup\$ – Ale..chenski Jan 25 '18 at 19:29

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