# What is a “half latch” in an FPGA?

In a paper about radiation hard FPGAs I came across this sentence:

"Another concern regarding Virtex devices is half latches. Half latches are sometimes used within these devices for internal constants, as this is more efficient than using logic".

I have never heard about an FPGA device primitive called a "half latch". As far as I understand, it sounds like a hidden mechanism to "source" a constant '0' or '1' in the backend tools... Can anyone explain what exactly a "half latch" is, especially in the context of FPGAs, and how they can be used to save logic?

EDIT: The paper were I found this was A Comparison of Radiation-Hard and Radiation-Tolerant FPGAs for Space Applications

• Which search engine did you use? – Ale..chenski Jan 25 '18 at 15:05
• It's a fault that is reported in the design stage that requires corrective action slideserve.com/delilah/single-event-upsets-in-sram-fpgas due to accelerated stress, like a bit error internally except it latches and can make a tristate into an output for example – Tony Stewart Sunnyskyguy EE75 Jan 25 '18 at 15:27
• @TonyStewart.EEsince'75 Faults are used for internal constants? That doesn't make sense. – duskwuff Jan 25 '18 at 18:24
• No. Half-latches are hidden faults that must be avoided. – Tony Stewart Sunnyskyguy EE75 Jan 25 '18 at 20:33
• @TonyStewart.EEsince'75 That still doesn't make any sense in context. The presentation you linked to clearly depicts a "half latch" as a part of the FPGA, alongside other things like "config bits" and "BRAM". It isn't a fault; it's something which can be affected by a fault. – duskwuff Jan 26 '18 at 0:30

A half-latch is a gate with positive feedback implemented with a weak pull-up transistor:

simulate this circuit – Schematic created using CircuitLab

When the input is actively driven, it overrides the signal coming from the weak pullup. When the input is in Z-state, the weak pullup can keep the logical "1" at the input (and "0" at the output) indefinitely. It will not keep the opposite state reliably, hence "half-latch".

Why would someone want a half-latch instead of a full latch? For some signals it doesn't make sense to be able to store both constants. For example, a D-flipflop can have enable input only latched high, and reset input only latched low, otherwise it will simply be eliminated during synthesis. That's the kind of signals for which half-latches are used: they are either latched to default value, or driven by interconnect.

• So you're supposed to drive the input high for a moment before floating it, or you will end up with a metastable state that will eventually but unpredictably flip? – Henning Makholm Jan 25 '18 at 23:56
• @HenningMakholm Yes, the FPGA drives all half-latches before each programming cycle. – Dmitry Grigoryev Jan 26 '18 at 21:37
• That sounds like a significant complication of whichever circuitry supplies the input, just to save a single transistor. If you could write something about why on earth that would be worth it, I think it would improve the answer. – Henning Makholm Jan 26 '18 at 21:49
• @HenningMakholm Why do you think a half-latches only save a single transistor? AFAIK they are used as constants which otherwise would have to be encoded in LUTs. – Dmitry Grigoryev Jan 26 '18 at 23:03
• A fully functional latch would only need a single weak NMOS in addition to your diagram to pull the input down when the output is high, right? I don't know what a LUT is -- can you say something in your answer about how "used as constants" works if the only thing it can store reliably is an 1? How are these things used? – Henning Makholm Jan 26 '18 at 23:07

It seems they provide the logic for keeping constants.

Since they are not observable, can only be initialised once (so only reconfigurable after device initialisation), they do not consume a full LUT and they are much simpler, nevertheless usefull.

• I saw that abstract text when I searched google, too. It doesn't properly explain them as per OP's question, nor lead them to a datasheet example. Downvoting. – TonyM Jan 25 '18 at 15:34
• If its a different structure of the FPGA and less than a full LUT, with a few more more specifics, then please explain how it does not answer the question 'what is it' and as for 'how it saves logic', that's also answered. – gommer Jan 25 '18 at 15:56