This gives you a TTL-compatible output signal that can also be pulled up to 12 V or much higher by an external load.
simulate this circuit – Schematic created using CircuitLab
You can then use the non-inverted drive signal in TTL mode but the inverted drive signal in IGBT mode. This can be done by modifying the signal at source or by XORing your relay control line with the drive signal.
The inverter needs to be able to drive your 50 mA at 5 V. From your question, you've found suitable logic gates for this anyway.
D1 protects the inverter from voltages above its supply, such as the coil 12 V if you drive that. It should drop around 0.7 V when the output is driving high. R1 limits the inverter output current during switching, when the IGBT may also be conducting. It should drop 0.5 V at 50 mA.
R2 ensures that the tiny leakage current through D1, when reverse-biased with 12 V, is leaked down to GND. This stops a potentially damaging voltage being put on the inverter output. The inverter will probably have an internal clamping diode between its output and its positive supply rail but I don't know which logic family you're using, hence R2. The absolute worst-case reverse-biased current for a 1N4007 is 50 uA, so the 10 K would only produce a 0.5 V drop if it was the only sink for that current, which it isn't.
The D1 and R1 voltage drops are approx. 0.7 V and 0. 5V when driving high at 50 mA. Then there's the drop in the logic gate output at 50 mA to consider. This should still give you a good TTL logic high (>2.4 V) out of the circuit.
If you decide that you want a stronger drive to a higher TTL high voltage than this circuit will give, you could use the below circuit instead.
simulate this circuit
Here, the high-drive is provided by a PNP running from a 6 V rail. The higher rail compensates for the 0.7 V and 0.3 V drops in D1 and Q2 respectively. So you get a strong 5 V output at 50 mA. If your load is fine with a TTL high of 4 V at 50 mA, you can use a 5 V rail, or select between 5 V and 6 V or whatever.
R3 and R4 are a potential divider, set to deliver Q2 a Vbe of 0.7 V to turn it on when the logic buffer output is 4 V or less. This means that Q2 is only on when Q1 is off. R3 and R4 draw a base current of around 600 uA, allowing for at least 60 mA output even with a low Q2 hFE of 100.
Incidentally, I did look at using a comparator for Q2 but the fewer freely-available, fast parts about with a >50 mA output were a few pounds. The buffer, PNP and two resistors plus sourcing and assembly costs will be much less. You'd previously that cost is very important here.