I'm developing on a small modular computer system using the Z80 just for fun. The backplane is a prototype PCB with five DIN41612 connectors wired in parallel, running about six inches from the first connector to the last. (This one: http://www.busboard.com/BB3U)

The CPU card I've made is composed of 74HCT-series logic and CMOS components (for SRAM, Flash, Z80, UART, etc.) all running at 5V. What kind of termination on the backplane would be ideal for a system like this?

The fastest signal on the bus is a 20 MHz system clock, everything else is in the 5 MHz range. The signals are mostly unidirectional, a few bidirectional for the data bus, and then some open drain signals for reset and interrupts inputs to the CPU card.

I've read about the VME bus which used Thevenin termination and it required strong drivers (74F-series to sink/source 24mA) over a very long backplane so that seems inappropriate here. But I'm not sure what else is appropriate.

  • \$\begingroup\$ What is your specific question? \$\endgroup\$ – Andy aka Jan 26 '18 at 16:09
  • \$\begingroup\$ Depends on your characteristic impedance from your drivers and the tracks on the backplane. Probably around 50 ohm if your drivers can support it. \$\endgroup\$ – winny Jan 26 '18 at 16:14
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    \$\begingroup\$ It sounds a bit like like S100, but faster. \$\endgroup\$ – Jasen Jan 26 '18 at 23:33
  • \$\begingroup\$ @Jasen: Thanks, I hadn't heard of S100 and it's very close to what I'm looking for. \$\endgroup\$ – user171804 Jan 29 '18 at 18:14

Transmission line effects create false transitions from ringing when the Return Loss or Impedance mismatch occurs from time delays greater than the rise time.

Generally 74HCT logic is rated with 50pF and Vol rated at 4mA for some Vol like 0.4Vmax with an input threshold of 2 TTL diode drops or 1.4~1.5V and may have a rise time of 15ns @ 50pF over all temps but best case may be faster.

Using impedance of the back plane tracks to ground, you can compute the track capacitance and also compute the time delay and decide what is worse.

  • 1) High impedance stripline with lower capacitance but higher inductance and high mismatch ?
  • 2) Low impedance ( 50~100 Ohms) with high capacitance going at 2/3c velocity with matched terminations..

Use a track capacitance , impedance, prop delay calculator and use a 74HCTxx driver impedance of 50 to 100 Ohms with an RC rise time to estimate if rise time is > time delay.

If you do need termination it still becomes a tradeoff but will likely be an R pair network resistor DIP or SIP or SOIC that biases to 1.5V with some impedance unless you choose 74ACxx or other family.

As your backplane is edge sensitive such as going to counters , latches, you will want to compute noise margin in the clock drivers.

I suspect the rise time is too slow, but they don't give best case specs.


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