In a lecture, my instructor told us that mosfets have various capacitances associated with them. eg for a switching application the important ones are- Gate-source cap, Drain-source cap, and Gate-Drain cap.

Now he said that during turn-ON of a mosfet a current flows through gate of the mosfet that charges all these 3 capacitances. The capacitance of these capacitors determine the turn-ON time of a mosfet. He gave the example of a N-channel mosfet.

While I was applying same concepts to a P-channel mosfet, I came across a doubt. In case of a P-channel mosfet, does gate-source cap. and all above caps. charge or discharge during turn-ON of a P-channel mosfet. It seems to me that caps. should discharge during turn-ON and should charge during turn-OFF.

Specifically, I'm driving a P-channel mosfet as High-side switch via a open collector output pulled up to 5V. So I need to know this. After searching through many docs on google and many books, I still have this doubt uncleared as all have examples of N-channel mosfet not a P-channel one.

Can anyone clear this doubt or provide any references or links?

The circuit is similar to this,

enter image description here

but components are different. If required, the mosfet I'm using is IRF9392.

Update1 on 2012-07-09 : PMOS Drive circuit

"This circuit will switch off slowly due to Resistive turn off gate drive. OK in most on/off cases - but not at smps frequencies. D3 not obviously useful."

In above schematic ckt. why D3 is not useful after adding a D2 schottky(Anode to Gate) and D1 zener(Anode to Gate) in parallel, physically and electrically close to Q2?

Why will turn-off be still slow(even with diode D3)? Is it due to resistor R4 or increase in gate-source capacitance due to zener and schottky?

Update2 on 2012-07-14:

Is a gate to source zener, like D1 zener(Anode to Gate) required, even with a flyback diode across an inductive load(instead of resistor R3) connected to drain of Q2?

up vote 3 down vote accepted

No, also for P-channel MOSFETs it's charging them. The confusion probably stems from the voltage you see at the lower side, which goes to ground (or near it). But that voltage isn't important, a capacitor's charge is determined by the voltage across it:

\$ Q = \Delta V \cdot C \$

So decreasing the gate voltage increases the gate-source voltage difference, which increases the charge of the capacitor.

When you switch off T1, there's current flowing from +12 V through R2 to the gate to discharge it's capacitance.

edit re the update of your question dd. 2012-07-09(*)
Turning off means that you discharge the gate to +5 V, and this happens by current through R2 and D3. So you bypass R? but R2 is still the limiting factor. A solution would be to swap R2 and T1, so that there's more current/less resistance to discharge the gate than to charge it.

\$ \$

(*) I'm using the ISO 8601 standard date format here. We have user from all over the world and for some 9/07 means 9 July, for others it's 7 September. ISO 8601 is unambiguous.

  • Got it :) This means that when I switch on T1, there will be a current flowing from gate of Q2 to Ground via T1's collector and emitter charging all 3 capacitors. Does this transient current (due to charging and discharging of capacitors associated with mosfet Q2) can affect the load in any way? Say I had a Relay(or any inductive load) instead of R3 in this ckt? I mean, will there be any transient current via load during turn-on or turn-off of Q2(except of course when mosfet is ON)? – jacks Jul 7 '12 at 12:06
  • @jacks - no, the capacitances are so low that they won't bother you. In the datasheet it says for instance gate-to-drain charge 4.1 nC, at the given voltage that's less than 1 nF. This will start to play a role if you want to switch fast like in PWM. – stevenvh Jul 7 '12 at 12:24
  • @stevenvh- I saw some circuits in which they place(and recommend) a zener diode between source and gate of Q2(anode at gate and cathode at source terminal) in parallel to R2. Is it necessary? Since as you pointed that the mosfet capacitances will won't affect the ckt at moderate switching, then I don't see a reason for placing a zener diode to clamp Vsg, or am I missing something here? – jacks Jul 7 '12 at 12:40
  • @jacks - I've never seen a diode there, but if you want to switch a relay or other inductive load you'll need a flyback diode across that load. – stevenvh Jul 7 '12 at 12:47
  • @stevenvh- I'm talking about something similar to this at this post and Fig3 at page# 2 in this doc and some more that I don't have link for. But they were all (except one or two) illustrated N-channel mosfets as is common practice to forget about P-channel mosfet :) – jacks Jul 7 '12 at 13:39

All capacitances charge during turn on and discharge during turn off.

The "polarity conventions" for a P Channel MOSFET are the opposite to tjhose for a N Channel MOSFET which can be confusing.

With an N Channel FET to turn it on you charge eg the gate-source capacitance by pulling the gate +ve relative to the source so that conventional current flows into the gate or electroncs flow out.

In a P Channel FET to turn it on you charge eg the gate-source capacitance by pulling the gate -ve relative to the source so that conventional current flows out of the gate or electrons flow into it.
With a P Channel FET

As Steven notes, the capacitors get charged either way
(you just have to turn your brain upside down).

Do this so your MOSFET will live :

I saw some circuits in which they place(and recommend) a zener diode between source and gate of Q2(anode at gate and cathode at source terminal) in parallel to R2. Is it necessary?

This is the main reason for my answering this question.
I ALWAYS use a gate to source zener (Anode to source) when there is an inductive load and tend to use one as a general rule when there is any chance that the load may be "interesting".

The role of the zener is to clamp the gate below the Vgs_max rating but not to affect it under normal drive conditions. This is because a large parasitic drain to gate "Miller Capacitance" can form * which couples the drain signal to the gate. If there is a fast and large drain positive transient (such as during inductive turnoff) this can be coupled into the gate circuit and drive Vgs above Vgsmax. Vgs max is typically 20V for most MOSFETS, around 10V for logic FETs and about 5V in the case of some specialist logic FETs with very low Vgs_th.
The gate rated voltage is a function of the gate oxide layer and it can be easily punched though by voltages only slightly more than rated value.
I had a product that would die within minutes when no gate source zener was fitted but would operate reliably indefinitely with a zener.

Some people use a gate-source Schottky diode - reverse biased during normal use. The purpose is to clamp negative going gate transitions at very low values and thus damp and stop parasitic gate ringing signals - which can cause great 'fun'.

Another way to damp these is to slip a ferrite bead over the gate lead.
However, when using a zener I have never been troubled with gate oscillations.
Both zener and Schottky could be used together if desired.


Miller Effect

The Miller effect is the appearance of a gate to drain capacitor of a valuye of about actual C_drain-gate x gain. As gain can be high the effective capacitance can also be dangerously high.

IR - Power MOSFET basics - by fig 10.

Existance and effect in valve amplifiers


Other:

Unlikely to be of direct relevance here but be aware of cascode mode used to overcome bad effects of Miller capacitance. Discussed at length here. Q1 is driven conventionally but drives the drain of the HV output stage in common gate mode. See article.

enter image description here


Added: Re your diagram.

Schottky and zener in parallel. Zener polarity needs to be reversed. Zener works when gate goes too low. Schottky when it rings high. Schottky and zener when used need to be AT gate and source - not behind R. Mount physically and electrically close to FET.
R limits turn on speed - reduces EMI and gate switching losses. Black art.

This circiuit will switch off slowly due to Resistive turn off gate drive. OK in most on/off cases - bot at smps frequencies.

D3 not obviously useful.

  • Hmmm... that seems to start clearing the fog. Thanks Russell. Actually I got confused through the models of N-channel mosfets I've seen. They almost all use polarized capacitor symbol to show these capacitances. So I thought they should be other way in case of P-channel mosfet. – jacks Jul 7 '12 at 14:22
  • Well, I skimmed through the docs you referred and it makes clear to me from your post what a general PMOS driving circuit should be, that takes care of most precautions mentioned in your post and those docs. Of course as Steven notes a flyback diode across an inductive load would be necessary, but other than that, take a look at this ckt, and tell me whether I need to add something else or that will suffice for moderate switching and in general. Diode D3 is for fast turn-Off. Well a picture is worth a thousand of words :) – jacks Jul 7 '12 at 14:27
  • One more thing. Whether diode D3 should be Schottky or small-signal? I think Schottky would be better or it will be an overkill? – jacks Jul 7 '12 at 14:31
  • @jacks - Your power supply is only 5 V. Unless you have a really low Vgs(th) I'd go for the Schottky. – stevenvh Jul 7 '12 at 14:41
  • "you just have to turn your brain upside down". So that you're upright again when you're in New-Zealand? :-) – stevenvh Jul 7 '12 at 14:41

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