Review request: DIY DC to 50MHz differential oscilloscope probe

Question

Given the cost of proper differential probes, i've decided to make my own. The requirements are:

• DC to 50 MHz 3db bandwidth
• A few selectable input voltage ranges, from 3V pk-pk to 300 V pk-pk
• Better than 1/500 common mode rejection ratio
• A "good enough" noise figure
• Realizable with the limited selection of parts from my local electronics store
• Layout feasible for a home-etched 2 sided PCB with hand soldered components.

I have little experience designing high speed analog circuits, so I'd love to receive feedback, including criticism, on the conceptual design. I also have a few questions regarding specific aspects of the implementation:

• Could I get away without impedance matching both ends of the coax, given how the carried signal would barely reach 50 MHz and the cable is under 1 m long? I'd prefer only terminating the scope end into 50 ohms (and directly driving the coax at the probe end), as a series resistor of 50 ohms at the probe end would divide the voltage seen by the scope by 2.

• Are the BJT current sources fast enough to sink a constant 5 mA given a high amplitude (3 V pk-pk at JFET gate) 50 MHz signal?

• Is the addition of an inductor between the source of each JFET and the collector of the corresponding BJT a reasonable way of ensuring a constant JFET drain current at higher frequencies, or does such a circuit inevitably oscillate?

• How sane is my PCB layout, are there any glaring shortcomings? What would you do differently?

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For supporting various voltage ranges, my preliminary design relies on external passive attenuators which plug into the 3 pin header connector (J1). The attenuators will have trimmer resistors and capacitors for matching the inverting and non-inverting inputs over the entire frequency range. Illustrated below is a 1:10 attenuator (roughly +/- 30 V range).

^{simulate this circuit – Schematic created using CircuitLab}

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The amplifier front-end is realized with JFET source followers in order to provide a high impedance to the attenuator stage. This topology was selected in order to circumvent the relatively high input bias current (worst case 2μA) of the available op amp. Bipolar transistor current sources ensure a relatively stable drain current to the JFETs over the whole input voltage range.

The op amp -based differential amplifier is also responsible for driving 1 m of RG-174 50 ohm coax. While the op amp is advertised as being able to drive coax directly, there are footprints for termination resistors.

Power is delivered by a 9 V battery, with the other half of the op amp acting as a virtual ground source. A red LED performs the dual function of indicating that the probe is on, and providing a ~1.8 V bias voltage for the current sources.

Components:

• Low leakage (< 5nA), 2pF input protection diodes: BAV199
• JFETs: SST310
• BJTs: BC847b
• 70MHz GBW, 1kV/μs dual op amp: LT1364
• 4x precision resistors (0.1%, 2.2kΩ) for the diff amp section.

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Answer 1

After actually building the thing

I can finally answer my own question in hindsight. I've built the circuit as featured in the question, with a 1:10 attenuator.

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• Could I get away without impedance matching both ends of the coax...

  Yes, but signal integrity does suffer from doing so. The blue trace is a ~6 ns rise and fall time square wave (generated by a 74HC14-based relaxation oscillator) as measured with a standard 1:10 passive probe. In the first four screenshots the yellow trace is the output of the DIY differential probe, multiplied by 10 by the scope, as connected in the diagram. The last screenshot is the SMA connector being probed directly by another 1:10 passive probe. The scope is a 50 MHz Rigol DS1052E, with 1MΩ 15pF inputs.

  

  As can be seen, terminating both ends results in a clean signal without overshoot, but with only roughly 13 MHz of bandwidth. The fastest rise time is achieved by avoiding loading the opamp, indicating that a low load impedance slows the opamp down very severely.

• Are the BJT current sources fast enough to sink a constant 5 mA...

  Yes. The JFET buffers and their biasing current sources perform flawlessly when it comes to frequency response. The bandwidth is bottlenecked by the opamp choice.

• Is the addition of an inductor between the source of each JFET and the collector of the corresponding BJT a reasonable way of ensuring a constant JFET drain current...

  It wasn't necessary, so I didn't try. No idea.

• How sane is my PCB layout...

  I had no problems relating to the layout itself, but I absolutely should have designed the board with mounting to a shielded case in mind. Heat shrinking absolutely won't do, the very high impedance circuitry is very susceptible to all kinds of interference. Even moving my hand under the table the probe sits on affects measurements by capacitive coupling.

An unforeseen deficiency with my design is the inability to correct for output offset voltage. Turns out, JFETs are unique snowflakes: The Threshold voltage can vary by several hundreds of millivolts, even in transistors from the same batch. When I first built the probe, it output +600 mV with the probes shorted together. I unsoldered the JFETs, tested all that were in my parts box and soldered the two that best matched each other to the board. Now the offset is a smaller, but still significant +30mV. Future revisions should have a mechanism for compensating for this offset voltage with a trimmer pot.

Another problem is the input voltage range. Negative voltages are handled linearly down to -30 V and below, but positive voltages above +6 V (attenuated to +0.6 V) gradually induce more and more distortion. This is caused by the JFET source followers saturating as they hit the positive supply rail, exacerbated by the gate-drain threshold voltage of -2.1 V, which means that a 0 V input already causes a +2.1 V output.
The proper fix is to bias the attenuators to -2.1 V instead of ground.

Answer 2

You have done a lot of good work here.

But the parts you have chosen cannot possibly meet your spec.

Do you have any design specs?
Step %overshoot ( on cable terminated with 50R) , gain error 0~50MHz, DC offset, Pwr, on/off switch? ESD protection level? Shorting Pins for storage?

Do you think the BAS diodes will be fast enough to protect the FETs from ESD with direct connection? I remember in '80's lots of young EE's blowing the front end FETs on Tek FET buffered Diff Probes that blew with 25V. I would add series R to limit current to input and replace BAV99's with TI's ESD diodes. 0.5pF TPD1E04U04. The Diodes must conduct faster than the FETs to protect them and ESD can be 10's of amps for picoseconds.

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I might have considered the Evaluation Kit for Layout of the AD8001.

16 In stock for FREE next working day delivery £8.04 From RS Electronics

Specs: 1.5pF input capacitance 800 MHz GBW, PSRR >50dB

Choose x1 x10 gain with onboard gain select.
Pref use 50 Ohm cable and 50 Ohm terminator for full bandwidth 800MHz to 80MHz.

Use Tektronics Diff Fet Probe mechanical design for probe pins. Although newer Tek models start at $6k they operate upto x GHz ranges. But for handheld and disposable solder leads consider their probes.

Since it is a current feedback chip, the input impedance is unconventional
+Input 10 MΩ
–Input 50 Ω