Using generate statement in Verilog

Question

I am using nested for loops using generate module for creating multiple instances of sub-modules in verilog this is for finding 4x4 determinant. I generated the sub-modules with inputs given accordingly but I want store outputs in array register serially from (1 to 6) as it runs 6 iterations in tempu[1:6] and tempd[1:6] but generate is not allowing to do so. I tried all the possibilities

    module det_4x4_v2(    
         input signed [15:0] a11,a12,a13,a14,a21,a22,a23,a24,a31,a32,a33,a34,a41,a42,a43,a44,
         output signed [15:0] out
        );       
     wire signed [15:0]  v1[1:4];   
     wire signed [15:0]  v2[1:4];
     wire signed [15:0]  v3[1:4];
     wire signed [15:0]  v4[1:4];   
     wire signed [15:0] tempu[1:6];
     wire signed [15:0] tempd[1:6];

    assign v1[1]=a11;
    assign v1[2]=a12;
    assign v1[3]=a13;
    assign v1[4]=a14;

    assign v2[1]=a21;
    assign v2[2]=a22;
    assign v2[3]=a23;
    assign v2[4]=a24;

    assign v3[1]=a31;
    assign v3[2]=a32;
    assign v3[3]=a33;
    assign v3[4]=a34;

    assign v4[1]=a41;
    assign v4[2]=a42;
    assign v4[3]=a43;
    assign v4[4]=a44;

    genvar i,j,count;

    generate

       //localparam count=0;

      //for(count=1;count<7;count=count+1)

    for(j=1;j<4;j=j+1) 

    begin:gen_det2x2_sub1

          //localparam count=0;

     for(i=j+1;i<5;i=i+1)

         begin:gen_det2x2_sub2

         det_2x2 m1(v1[j],v1[i],v2[j],v2[i],tempu[count+1]);
         det_2x2 m2(v3[j],v3[i],v4[j],v4[i],tempd[count+1]);

         end
    end      
    endgenerate      




assign out = ((tempu[1]*tempd[6])-(tempu[2]*tempd[5])+(tempu[3]*tempd[4])+
              (tempu[4]*tempd[3])-(tempu[5]*tempd[2])+(tempu[6]*tempd[1]));  
                            // above equation want to implement-------(1)

    endmodule


/*    det_2x2 m1(v1[1],v1[2],v2[1],v2[2],tempu[1]);  //finally want to generate 
      det_2x2 m1(v1[1],v1[3],v2[1],v2[3],tempu[2]);   // these modules
      det_2x2 m1(v1[1],v1[4],v2[1],v2[4],tempu[3]);
      det_2x2 m1(v1[2],v1[3],v2[2],v2[3],tempu[4]);
      det_2x2 m1(v1[2],v1[4],v2[2],v2[4],tempu[5]);
      det_2x2 m1(v1[3],v1[4],v2[3],v2[4],tempu[6]);

      det_2x2 m2(v3[j],v3[i],v4[j],v4[i],tempd[count]); // same way as above m1 
                                                                   module


*/    

module det_2x2( 
 input signed [15:0] a11,a12,a21,a22 ,
 output  signed [15:0] out
    );

 wire signed [15:0] temp;

 assign temp = (a11*a22)-(a12*a21);

 assign out = temp ;    

endmodule

the sign of each term in equation 1 depends on (-1)power(i+j) in each iteration and should me multiplied with `tempu or tempd' in the particular iteration.

i can implement these manually (instatiate manually and write out equation (1) manually) but its difficult when doing for higher order matrices where for (8x8) it takes 70 modules for instantiation.

please help me in assigning the temp,tempd registers continuously indexed for the above nested loops.

thank you

Answer 1

You can't use a 'free' generate variable 'count' thus the only solution I can come up with is to express the index of tempu and tempd in terms of i and j. This is how your j,i go:

[j,i] = [1,2] [1,3], [1,4]   required Index:  1, 2, 3
        [2,3] [2,4]                           4, 5
        [3,4]                                 6

The best I can come up with is:

det_2x2 m1(v1[j],v1[i],v2[j],v2[i],tempu[ j==1? i-1 : j==2 ? i+1 : 6]);
det_2x2 m2(v3[j],v3[i],v4[j],v4[i],tempd[ j==1? i-1 : j==2 ? i+1 : 6]);

But it is clumsy and very specific to this code. As soon as the upper limit of the for loop changes that is no longer valid.

It passes a quick syntax check in Vivado, but can't fully check it because I have no det_2x2.