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In my lecture notes I keep reading "do not gate the clock". I tried searching on the Internet, but I'm unable to find the exact meaning of this phrase.

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    \$\begingroup\$ en.wikipedia.org/wiki/Clock_gating \$\endgroup\$ – BeB00 Jan 27 '18 at 22:21
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    \$\begingroup\$ @user129048 there are other questions that deal with this subject on this site. In short, if you gate the clock you will have a delay which is bad. Most FPGA's have dedicated clock lines, and gating the clock will not use those lines. \$\endgroup\$ – Voltage Spike Jan 28 '18 at 1:22
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    \$\begingroup\$ Just like you use a gate to let your dog/horse/etc in and out, they can pass through if the gate is open. Clock and reset are just signals that are passed on to a module of logic just like the other signals. You can allow or block that clock from continuing, not letting it pass. Preventing the logic on the other side from having that signal as an input. \$\endgroup\$ – old_timer Jan 28 '18 at 2:14
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To "gate the clock" means put a logic gate in the clock line to switch it on or off.

schematic

simulate this circuit – Schematic created using CircuitLab

The diagrams above show and AND and OR used to gate the clock. One forces the clock low the other high.

To prevent clock pulses which are 'too short' either high or low ("runt pulses"), we must make sure that:

  • The control signal for the AND gate should change only when the clock is low.
  • The control signal for the OR gate should change only when the clock is high.

Gated clocks are very useful for reducing power in CMOS as the logic stays 'quiet' while the clock is stopped. You will find that modern synthesis tools have special option to insert clock gating automatically.

schematic

simulate this circuit

Above are two circuits which safely generate a gated clock. The circuits rely on the fact that there is as a small delay (clock to Q) for the control signal to come out of the register. Thus the control signal changes at the gate when the clock has a known polarity.

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    \$\begingroup\$ Very nice answer. I'll just expand on the power benefits of gated clocks. The clock network in an IC, especially in complex ones like microprocessors, can be really vast. So vast that it has been shown (sorry I don't have the reference at hand) that the switching of the clock network alone can make up 30% of the total power consumption. This is consumed even if the actual logic clocked by it has nothing to do, eg. the registers and outputs don't change at all. Gating the clock can disable the clock completely in the affected parts of the network, hence significantly reducing power consumption. \$\endgroup\$ – ultimA Jan 27 '18 at 22:46
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    \$\begingroup\$ @Curd: When the OP reads "do not gate the clock", the professor means "do not gate the clock literally as in with a single logic gate". That is good advice. In practice though "clock gating" means "disabling the clock" or being able to do that, and it is very much recommended to do so for power reasons as long as you know how to do it correctly (that is, not with a logic gate, but with sufficient logic to avoid runts and glitches on the clock line). \$\endgroup\$ – ultimA Jan 27 '18 at 23:19
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    \$\begingroup\$ I have to guess here why the professor says this: clock gating, although presented here as simple, has many pitfalls. Therefore it is very much frowned upon. In ASIC design (where I come from) it is only done by either the tools, which are supposed to be trusted, or by principal senior engineers, also assumed to be trusted to know what they are doing. \$\endgroup\$ – Oldfart Jan 28 '18 at 0:21
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    \$\begingroup\$ @oldfart That is very likely the explanation. Especially if OP is in an FPGA class, its unlikely they should ever be gating a clock. \$\endgroup\$ – mbrig Jan 28 '18 at 2:20
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    \$\begingroup\$ @MITURAJ, clock gating most certainly can be done in design entry. I think you're describing what should be done, not what's 'usually' done. The freedom of FPGAs allows anyone to implement bad ideas. Lot of bad designs out there. \$\endgroup\$ – TonyM Jan 28 '18 at 9:04
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Gating, in this context, means to pass a signal through a logic gate to control it.

Passing it through one input of a 2-input AND gate allows a control bit on the other input to force the AND gate output low or to let the signal pass through and out. A similar function can be done by an OR gate, with the signal being forced high or let through.

So gating a clock means forcing it low/high or letting it pass through.

Not gating clocks is good advice. It can be done, with care and thorough understanding of the possible consequences. These include metastability when taking clocked signals into the gated clock domain and worse results from timing-driven synthesis/layout.

But there are nearly always other ways to achieve the same control over a circuit as gating the clock, without all such risks and penalties.

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It means:
Do not use an AND or OR gate (or any more complex combinatory term) to derive a clock signal from another clock signal.

The reason for that rule is that race conditions among the multiple inputs of the combinatory term may cause multiple clock edges (glitches) where you expect only one clock edge.

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    \$\begingroup\$ It would be nice if the downvoter would be able to explain what he consideres wrong with this answer. \$\endgroup\$ – Curd Jan 27 '18 at 23:03
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For high speed it implies do not add logic gates which add propagation delay to the clock as it may cause race conditions with working with data using original clock.

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  • \$\begingroup\$ I've never heard the term clock gating used this way, do you have a source for that? \$\endgroup\$ – BeB00 Jan 27 '18 at 22:33
  • \$\begingroup\$ @BeB00: just google for "clock gating glitch free" and you will find plenty \$\endgroup\$ – Curd Jan 27 '18 at 23:09
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    \$\begingroup\$ google.ca/… \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Jan 27 '18 at 23:24
  • \$\begingroup\$ This was my first thought not having heard the term used before but there are times that buffering will be needed and gating probably is intended to mean more than buffering in this case. Slew and edge characteristics may change with simple buffering and need to be considered in any event. \$\endgroup\$ – KalleMP Jan 28 '18 at 19:08

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