You can indeed use initial values in Verilog or VHDL but they reduce the portability of your design. They are therefore to be avoided and are not recommended.
Your design will behave differently depending on the target device. Synthesize it for a RAM-based FPGA (typ. Altera, Xilinx) and your design will work because the initial values will be recognised.
Synthesize it for a Flash-based FPGA (typ. Microsemi), a CPLD (typ. Altera, Lattice) or an ASIC and your design won't work because initial values are meaningless. The cause will not immediately be apparent, particularly if it isn't your own design, so there's engineering time and cost in discovering it and reworking it.
Use a reset. RAM-based FPGAs provide asynchronous (or, less commonly, synchronous) resets on their DFFs, so it costs you routing but not resources. The design is now portable across all CPLDs, FPGAs and ASICs.
Each target device now needs to provide a reset for itself.
This might be externally generated, then passed through a simple input stage to make an asynchronously asserted, synchronously negated, reset that avoids metastability in DFFs on negation.
Or it can be internally generated in a RAM-based device, using a simple n-bit (I use 4-bit) shift register with an initial value of '0's and shifting in a '1'. An initial value can be used here on this shift register, and here alone, because (a) it results the same reset signal to all DFFs as an external reset would and (b) this is the only part to change if a different device is targeted. All other Verilog/VHDL remains completely unchanged in a device re-target.
Initial values have pitfalls and can cause invisible problems. A reset does not and will not.
I could say it's up to the professional designer as to their choice...but it's not. Because, unless working completely alone, they don't pay for the development or bear the costs of the consequences.
If you're designing professionally then you should be delivering the most problem-free designs to your employer or client, and that includes portability. You're also making harder to re-use your own designs if you work elsewhere in a year, five years or ten years, on different devices. The design owners (your employer or client) will expect other engineers to be able to re-use your designs that they paid for, in different products with different target devices.
The fact that your design synthesized and worked here is proof of nothing, I'm afraid. In engineering, it is very easy to make designs that work. (Think of that bloke whose shelves are barely hanging up with one nail but still there.) Our goal is to make designs that never don't work. In digital circuit design, this is one way to make that much more likely.
Many clients I have worked for simply ban initial values in their coding standards for all these reasons. The majority of IP you'll find, especially PLD vendor IP, uses resets for the same reasons.
In summary: don't use initial values. Keep your designs portable. Keep yourself mobile across jobs and industry. Lessen everyone's fault-finding.