I am designing 8 point FFT by radix 2 using verilog. I am using radix 2 butterfly unit with 8 bits input and so output. I expect to be 8 bit so that I can use this structure again and again for further sta. I am applying DIT. If I consider my twiddle factors are of 8 bits stored somewhere then I multiply to one of butterfly inputs result is 16 bits, and when added/subtracted to other input output is for sure going to be min 16 bit/ 17 bit. But I expect my output to be of 8 bit so that same butterfly with 8 bit input can be used. How do I scale this without loss of accuracy
module butter_fly(xr,xi,yr,yi,wr,wi,xxr,xxi,yyr,yyi); input[7:0] xr,xi,yr,yi,wr,wi; output[7:0] xxr,xxi,yyr,yyi; wire[7:0] xxr,xxi,yyr,yyi; wire [7:0] xr,xi,yr,yi,wr,wi; // wr and wi represents twiddle factor wire[15:0] w1,w2,w3,w4; assign w2 = yi*wi; assign w3 = yr*wi; assign w4 = wr*yi; assign w1 = yr*wr; assign xxr = xr + w1 - w2 ; assign xxi = xi + w3 + w4; assign yyr = xr - w1 + w2; assign yyi = xi - w3 - w4; endmodule
I am exceeding these 8 bits in my ouput. since these output will become input to my next stage. the next stage also consists of radix 2. This obtained output I can not feed into it. It has to be 8 bits. So how do i scale this output of butterfly so that it can become 8 bit type input to next stage butterfly unit. I expect my final output to be correct at last.
let me know if you do not understand