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Consider the simple circuit schematic below:

enter image description here

1) Would a high voltage (say 1kV-25kV) human body ESD discharge event (1ns rise time, 100ns total) at OUT have a negative effect (damage or destroy) the electrolytic capacitor when in the polarity as shown?

2) Do ESD events in general cause issues when using electrolytics with the polarity such that the + plate is facing the high voltage spike (positive polarity)? Or does the spike need to be clamped approximately to the capacitor's rated voltage for proper reliability?

I haven't been able to find much information about this.

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    \$\begingroup\$ During ESD testing, pulses of both positive and negative polarity are used. So polarity matters very little. But the charge reservoir used for ESD testing is only 100pF. That is too small to cause much of a voltage change on a 100uF cap. Basically it is a 1,000,000 : 1 voltage divider. So 10kV discharge will only cause 10mV voltage change on the cap. If you wanted to, you could move R2 closer to "OUT." Usually, it is silicon that gets damaged by ESD. Not passives. \$\endgroup\$ – mkeith Jan 28 '18 at 17:23
  • \$\begingroup\$ If you are concerned, put R2 closer to "OUT" and put a small ESD diode (TVS diode) in shunt between R2 and C1. But I don't think you have anything to worry about. \$\endgroup\$ – mkeith Jan 28 '18 at 17:29
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    \$\begingroup\$ As @mkeith mentions the cap will hardly notice the event. Actually I would be more concerned about the resistors than the cap and even more so about whether is driving V1. The cap is just going to pass along the spike. i.e. when the right side goes to 25K so will the left. \$\endgroup\$ – Trevor_G Jan 28 '18 at 18:08
  • \$\begingroup\$ Why would you put the TVS diode shunted between R2 and C1 as opposed to between OUT and COM, assuming high enough ESD source resistance to limit the current somewhat? \$\endgroup\$ – User7251 Jan 28 '18 at 18:11
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    \$\begingroup\$ Yes. If V1 is actually an audio output DAC, then V1 might get damaged. But now we need to consider if the electrolytic cap can actually be modeled as a cap when it comes to an ESD pulse. There may be substantial parasitic inductance. It all gets messy. That is why people tend to just slap down an ESD diode and move on. Series resistors and ferrites also help attenuate the ESD pulse. \$\endgroup\$ – mkeith Jan 28 '18 at 18:15
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During ESD testing, pulses of both positive and negative polarity are used. So polarity matters very little. But the charge reservoir used for ESD testing is only 100pF (or 200pF depending on the model). That is too small to cause much of a voltage change on a 100uF cap. Basically it is a 1,000,000 : 1 voltage divider. So 10kV discharge will only cause 10mV voltage change on the cap.

If V1 is actually an audio output DAC, then V1 might get damaged. But now we need to consider if the electrolytic cap can actually be modeled as a cap when it comes to an ESD pulse. There may be substantial parasitic inductance, so it may even help protect V1 for all I know. It all gets messy. That is why people tend to just slap down an ESD diode and move on.

Series resistors and ferrites also help attenuate the ESD pulse, and are seldom, if ever damaged by the pulse. So my philosophy has always been to put resistors or ferrites close to the ingress point of the ESD pulse, and put shunt protection close to the IC or transistor being protected. The more series elements you put between incoming pulse and silicon, the better. For signals with no high frequency content, a simple RC filter may provide great protection from ESD.

Getting back to your circuit. If you wanted to, you could move R2 closer to "OUT," and put a small ESD diode (TVS diode) in shunt between R2 and C1. This would be to protect V1. Since you haven't told us what V1 is, I don't know whether it needs protection or not.

When trying to filter high frequencies, we tend to look at ferrite beads. But a 10k SMT resistor has higher impedance from DC to microwave than any ferrite bead, and they are cheaper, too.

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