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I am testing my setup of MCP4725 DAC connected to MCP3221 ADC. DAC's output is connected to ADC's input. I'm measuring the difference between set values in DAC and measured values in ADC and I'm getting these strange patterns.enter image description here Edit:x axis: values set in DAC (bits), y axis: DAC value - ADC value (bits)

Minimums and maximums are repeating every 128 bits. Also, errors shift from positive to negative going through the full range. I have tried different delays between setting DAC value and measuring ADC value and I get the same result. So I think it is not background noise.

Edit2:Schematics: enter image description here

I use REF3033 to power both ADC and DAC. But the same pattern is present when connecting them to LF33CV. Also, adding additional capacitors betwen input/output and ground doesn't change the pattern, just shifts it up or down.

Could you please help me figure out why is this happening and how to avoid it? I'm really sorry if this is something basic I'm missing here.

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  • \$\begingroup\$ Take a good multimeter and measure the voltages for values with just one bit set \$\endgroup\$
    – PlasmaHH
    Jan 28, 2018 at 18:38
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    \$\begingroup\$ What range of different delays? \$\endgroup\$
    – Trevor_G
    Jan 28, 2018 at 18:43
  • \$\begingroup\$ @PlasmaHH unfortunately I don't have a good multimeter on hand . However, measuring one bit with my ADC I see max 2 bit oscilations, so it doesn't explain the pattern. \$\endgroup\$
    – Domas
    Jan 28, 2018 at 18:52
  • \$\begingroup\$ @Trevor_G from 10ms to 500ms \$\endgroup\$
    – Domas
    Jan 28, 2018 at 18:52
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    \$\begingroup\$ DAC datasheet page 3 says output impedance is 1 ohm which is fine. BUT ...page 2 says "INL Error (max) +/-14.5 LSBs". This is pretty appalling. Your plot shows about +/-4 LSBs, double the "Typical" spec on same page but much less than the guaranteed max. Also see Fig 2.5 p.5, same basic pattern (in some ways worse). That might be all you get unless you use a better DAC. (update : ADC spec looks OK) \$\endgroup\$
    – user_1818839
    Jan 28, 2018 at 20:16

1 Answer 1

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DAC output voltage accuracy can be estimated by looking at the data sheet and the output error limits: -

enter image description here

Then you need to understand what terms like INL mean: -

enter image description here

The graph above shows INL (integral non-linearity). Basically, it means that the DAC output could have to +/- 14.5 least significant bits of error from the ideal straight line. Given your DAC is 12 bits (4096 LSBs), the INL produces an error of +/- 0.35%.

But you will also have a zero and a gain error: -

enter image description here

The gain error can be up to 2% of full-scale and the offset error can be up to 0.75% of full-scale.

You can also get an understanding on the error patterns if you delve deaper into the data sheet. For instance this graph on page 5 shows the effect of INL and notice how certain patterns repeat as per the picture in the question: -

enter image description here

Remember also this is just the DAC - a similar picture will exist for the ADC.

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