The next schemtaic I was found as an input stage of ultra-linear phono amplifier.

enter image description here

  1. What are the benefits of that type of biasing? I don't see that 12V zener has 12V voltage drop on it (only 4.2V) and in this situation how I can predict the Q-point of JFET?

  2. What JFET's may be used with such schematic? I take JFET 2n4391 and the voltage gain of the stage drops dramatically.

  • 2
    \$\begingroup\$ You are quite right, Q point is practically unpredictable. it's not an ultra linear phono preamplifier, it's an ultra-bad phono pre :D \$\endgroup\$
    – carloc
    Jan 29, 2018 at 8:35

1 Answer 1


The idea of the circuit is that the Vds of the JFET is kept constant at about 12 V (more accurately: 12 V - Vbe_q2 = 11.3 V). Keeping the Vds constant eliminates any influence Vds has on the voltage-to-current transfer (Id / Vgs) of the JFET.

If you do not have 12 V at the cathode of the zener D1 then the circuit is not biased correctly. Then most of the current flowing through R2 goes into the base of Q2 and then to Q1.

Solution: lower the value of R2. D1 is a 1 W zener diode so it can handle 1 W /12 V = 83 mA. Let's say we use 20 mA through R2: 20 V - 12 V = 8 V, 8 V / 20 mA = 400 ohms. Hmm, that's a lot less than the 4.7 kohm you have.

What JFETs you can use depends on the JFET's properties. Look in the datasheet what the Id will be when Vgs = 0 as that is how the JFET is biased here.

I expect that you will also have to lower the value of R1 if you use a JFET with a Vgs=0 current of more than 8V / 2.4 kohm = 3 mA. Lowering R1 will also reduce the voltage gain though.

As an input for a low distortion phono amplifier, I have my doubts about this circuit. To really have low distortion you cannot beat feedback. A good solution could be a JFET based differential pair to provide a limited amount of gain. Then an opamp or opamp like circuit and overall feedback. That will hands down beat this circuit distortion wise.

  • \$\begingroup\$ 2SK170 datasheet tells that Id will be near 9ma when Vgs = 0V but how it can work when Id has only 3ma current? And why 2SK170 datasheet tells that minimal Idss near 2.6ma but I'm working now on more that 3ma to 10ma? \$\endgroup\$
    – MaxMil
    Jan 29, 2018 at 9:23
  • \$\begingroup\$ but how it can work when Id has only 3ma current? Like I wrote: it will not. You will have to lower the value of R1 such that 3.3 mA can flow while taking care that Q1 still has enough Vce. The datasheet states that Idss is between 2.6 mA and 20 mA so 3.3 mA is still in that range. Idss just varies a lot and the manufacturer has little control over it. That's one of the reasons JFETs are not used like this (relying on Idss), Idss just varies too much. When used in a differential pair, the Id is set in a different way (using a current source for example), that gives more control. \$\endgroup\$ Jan 29, 2018 at 9:32
  • \$\begingroup\$ Can you show sample two-stage JFET amplifier schematic with JFET differential input stage and one voltage amplifier stage on JFET with current source for stable bias and feedback loop? \$\endgroup\$
    – MaxMil
    Jan 29, 2018 at 18:15
  • \$\begingroup\$ Here's one: data-odyssey.nl/Super_TIS.html figure 16. How did I find that? I Google for "JFET input amplifier" then click the "images" tab and look for the right schematic. \$\endgroup\$ Jan 29, 2018 at 18:37
  • \$\begingroup\$ If the Drain-Source voltage is fixed then the DC part of that doesn't vary but what about AC - is it correct that it's vary and adds to fixed DC part according to superposition principle? \$\endgroup\$
    – MaxMil
    Jan 31, 2018 at 9:02

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