Peak power pulse in parallel MOSFETs

I have a circuit like the one shown below. To make the schematic easier to read, I only show 2 FETs in parallel. I actually have 8 identical FETs in parallel. The HT0440 is a high-side N-channel FET driver. It's controlled by a digital signal from an MCU.

simulate this circuit – Schematic created using CircuitLab

Power is not switched on and off rapidly in this application, but I am still concerned about the instantaneous heating in the FETs when power is turned off. Particularly when RLoad is small and the current is high prior to being switched off. I probed the source pins of the FETs during a switch-off event and observed this curve:

It takes about 250ms for the FETs to fully turn off. RLoad in this case was 10 Ohm. I did some calculations in a spreadsheet and came up with this curve for power-vs-time in the MOSFETs during the switch-off event:

Integrating under the curve, I get about 17Ws (Watt-seconds). That's the total accumulated power loss among all 8 MOSFETs. There's a graph in the MOSFET's datasheet that shows the maximum single pulse power dissipation as a function of pulse width.

Now, I know that MOSFETs in parallel will work "nicely" with each other to share the total current because of their PTC nature. However, I don't know if it's safe to assume they will continue to work nicely together during a switch-off event. In other words, as the gate pins are being driven low, is there some property of MOSFETs that would cause one single MOSFET to end up taking the brunt of the switching power dissipation? Or will they all share the total power dissipation equally?

• Must use individual gate resistors! Don’t repeat my mistake. How do you bootstrap the gate voltage? Jan 29, 2018 at 22:13
• @winny, the HT0440 has internal bootstrapping (or something equivalent). It's specifically designed for the purpose of driving high-side N-FETs. Jan 29, 2018 at 22:33
• Those MOSFETs of yours have a pretty large gate capacitance compared to the 600pF the HT0440's datasheet timing specs are measured with. When you stack 8 of them in parallel I'm not surprised it takes so long to turn them off ... Jan 29, 2018 at 22:45
• @brhans, yep, I've concluded the same thing. I plan to keep the MOSFETs because of their superior Rds(on) and Vds for this application, but I'll probably spec out a different gate driver for the next revision. Something that can push and pull a little more current. Jan 29, 2018 at 22:48
• The MOSFET is operating in linear mode, you need to look at SOA curve on the data sheet, not single pulse power. Paralleling MOSFETs does not help SOA because their is no guarantee that their linear characteristics will all be the same, so you have to use SOA for a single MOSFET. Jan 29, 2018 at 23:40

In other words, as the gate pins are being driven low, is there some property of MOSFETs that would cause one single MOSFET to end up taking the brunt of the switching power dissipation? Or will they all share the total power dissipation equally?

Your suspicions are correct. The normally nice side of MOSFETs sharing current only applies when the gate source voltage is above a certain threshold called the zero-temperature-coefficient (ZTC) threshold. For the MOSFET you have chosen it is about 6.7 volts: -

Basically I took figure 5 and extended the curves to the ZTC threshold. At gate voltages lower than this a MOSFET will warm to destruction if not prevented in some way. Take for example the situation at 25 degC and the instant application of a gate voltage of 5 volts. Current will be about 40 amps and this will cause the junction temperature to rise rapidly and, within a few milli seconds it will have warmed to 150 degC and now will be taking about 140 amps. The junction will rapidly rise past the 175 degC limit and reach destruction temperature (about 650 degC) in a few more milliseconds.

Not all of the silicon die will warm this way. In modern HEXFETs there are a gazillion parallel small MOSFETs and the most vulnerable are those closest to the centre and farthest away from the "cooler" edge. You wil get hot-spotting and the central 10% of the die will take all this current and destruct unless there are limits to the current flow.

This can happen in less than 10 ms and you wouldn't even notice hardly the slightest external change in temperature on the case. In other words, heat sinks DO NOT prevent this happening.

So hot-spotting can happen in a group of MOSFETs and it can also happen in an individual MOSFET. Some MOSFETs are designed for operating in this area and IXYS make quite a few. The front page of the data sheet will tell you. If it says that the MOSFET is for switching applications then it is likely to be vulnerable; if it says it is for linear applications than it is likely suitable and, if you look at a suitable device's equivalent of figure 5 you will see that the curves are much tighter leading to very little extra drain current as the device warms.

Go google "thermal instability in MOSFETs" and please consider a MOSFET driver that can turn off the gate voltage in less than 1 ms. Those MOSFETs have a gate-source capacitance of 15 nF and 8 of them makes a total capacitance of over 100 nF. It may even be necessary to use several gate drivers.

• Are we allowed to post "<---- This guy gets it!"? Jan 30, 2018 at 16:06
• @winny feel free lol Jan 30, 2018 at 16:37

The driver has a fall time of 2ms driving 600pF to 10 volts, a charge of 6 nC. You've attached 8 MOSFETs with a worst-case gate charge of 273nC each, for a total of 2.2 μC. So you can expect it to take worst case 370 times longer than the rated fall time: 740 ms.

Worst case you need to assume one FET has a threshold voltage of 2.0V and the rest are 4.0V. So this one will turn off last and be in linear mode while the others are off. About half the gate charge is below the threshold voltage, so this will be for about 370ms.

From the datasheet, I got:

The flat part of that curve is where the FET really turns on and off. The exact turn-on threshold varies from FET to FET, and the FETs "drink up" a bunch of current at their turn on voltage. So, if the HT0440LG drives at a max current of 2 mA, and the FET needs 40 nC to turn on, that takes 20 us, so each FET stalls out the voltage rise and fall for 20 us. This means that, worst case, the FETs will turn off one at a time in order of their Vgs threshold. The only good part is they turn on in the opposite order.

Individual gate resistors on each FET can help equalize the distribution a lot. You also should have an active current sink on your driver, like a push/pull transistor setup, which will increase the current going in and out of the gates, and decrease the turn on/off times.

You want to turn on and off as quickly as possible, and 250 ms is very, very slow. A slow turn off, as mentioned in the comments, means the FET is operating in linear mode where the resistance is somewhere between 1 mOhm and inifinity, so the current is going through a much larger resistance. The resistive heating will heat the FETs up briefly, and cycling their temperature will speed up their failure.

• As I appreciate your attempt to address the shortcoming of my circuit design (that I already acknowledged in a comment above), this answer does not actually address the question I asked. My question is specifically asking whether or not the 8 FETs will equally share the switching power dissipation. Please read the question to the end. Jan 30, 2018 at 2:44
• They will turn on and off at slightly different times, so no. Each FET may turn off separately for 20 uS (assuming the turn off current is 2mA, which I don't think is the case for your driver), leaving one carrying the full load for its shutoff time Jan 30, 2018 at 2:46
• I’ve corrected your post from millisiemens to milliseconds. Jan 30, 2018 at 6:48