From reading the book titled "Advanced Chip Design practical examples by verilog", I faced some questions about when the Ethernet packet is read from the FIFO and how the rollback works for the Ethernet packet FIFO.
The chaper 8.3.4 of the book explains the reason why rollback is necessary in the FIFO in the aspects of reading a packet and processing its CRC; when the CRC calculated from the receiver doesn't match with the pre-calculated CRC attached together with the packet, it needs to rollback the current FIFO write pointer to the rollback write pointer (rollback_wrptr). Here, rollback_wrptr is the write pointer of the FIFO saved right before it starts to receive the packet.
And the book says...
At the end of the packet, when we find CRC does not match, we assert one-clock wide signal, rollback_wrptr that reloads the snapshot value to the main wrptr of the FIFO.
I am wondering why the book only mentioned about the write_ptr but read_ptr and read_ptr_rollback. To calculate the CRC, it seems that the packets should be read from the queue; it will consume some elements from the FIFO, which moves the read_ptr of the FIFO. Does the hardware logic prevent the receiver from fetching the data from the FIFO until the CRC calculation done in usual?
It seems that it should rewind the not only the write_ptr but also the read_ptr. If available, could I get some code implementing the FIFO with the rollback in verilog or VHDL?