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I have a PCB with a single-ended sinusoidal clock input via SMA connector. (It should come from an external, low-jitter clock source).

This clock is used at various places (as references) and hence jitter is the largest concern.

It enters multiple ICs (say 3 for now). The input to these ICs has to be sinusoidal. The input impedance of the clock inputs is capacitive (like CMOS inverters).

Considering signal splitting and matching, what is an appropriate way to split and distribute the clock?

  1. Can I just make a star connection from the SMA connector to the various destinations or do I need some sort of buffers? If yes, which? (the clock distributions I find are just based on inverters and hence not for sinusoidal clocks/low jitter)
  2. Is it enough to terminate once at the connector and use simple PCB traces to the destinations?
  3. Should the traces be such that the characteristic impedance is 50 Ohm or 50/#consumers Ohm or just as thin as possible?

Take as an example (IC1 & IC3 have a self-biased inverter as input and IC2 is a discrete CMOS inverter which is biased half-rail of its supply):

schematic

simulate this circuit – Schematic created using CircuitLab

PS: lambda/100 is 3cm for 100 MHz. I'm definitely not able to confine everything within that. However, say, 30cm (lambda/10) should be possible.

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The input impedance of the clock inputs is usually high (like CMOS inverters).

An input with a parasitic capacitance of 5 pF presents a reactive impedance of about 318 ohms at 100 MHz.

it enters multiple ICs (say 3 for now)

Ignoring transmission line effects that's about 100 ohms reactive input impedance.

Can I just make a star connection from the SMA connector to the various destinations or do I need some sort of buffers?

It all depends on the driving impedance of your 100 MHz source - if it is low enough and the sensitivity of the 3 receiving chips are low enough it should be OK without buffers. Buffers have input capacitors too!

Is it enough to terminate once at the connector and use simple PCB traces to the destinations?

It might be; 100 MHz has a wavelength of 3 metres and a general rule of thumb is you can avoid nterminations if the track/cable length is less than one-tenth.

Should the traces be such that the characteristic impedance is 50 Ohm, 50/#consumers or just as thin as possible?

It's probably not going to be a big problem given track lengths but if it were you would match to the impedance of the source and this might not be 50 ohms. You didn't state what it was.

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  • \$\begingroup\$ The answer opens new questions (rather than answering). All that's fixed is the source impedance at the other end of the SMA cable (50 Ohm). Is this "low" enough? And if I would use buffers - which ones? As stated, it is a sinusoidal signal (single ended) and jitter is the biggest concern (it is used as references in various places). Hence adding buffers potentially adds jitter (particularly inverters) \$\endgroup\$
    – divB
    Jan 30, 2018 at 21:44
  • \$\begingroup\$ In any case, I interpret your answer as YES, MY CIRCUIT IS OK, NO BUFFERS/TRANSMISSION LINES NEEDED as long as the traces are <30cm and the source has 50 Ohm. Is that correct? \$\endgroup\$
    – divB
    Jan 30, 2018 at 21:45
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    \$\begingroup\$ No, that isn’t what you should infer. I have given answers to basic questions raised by you yet I know nothing about your circuit because you have given no great detail. \$\endgroup\$
    – Andy aka
    Jan 30, 2018 at 22:16
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It sort of depends on how you are using the clock - if the chips that are being driven use the clock to synchronise data between themselves then you want to minimise clock skew by carefully matching traces

If the traces are not short you probably also ought to serial terminate them to stop ringing

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    \$\begingroup\$ This does not answer the question but is another good thing consider. As stated, jitter is the most important concern, skew is secondary as long as their relative timing is exact. I updated my question to make things a bit more clear. \$\endgroup\$
    – divB
    Jan 30, 2018 at 21:52

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