This may "yet another" question about decoupling but the question is pretty precise and I can not find an answer.
I have a 40 pin QFN where I need to fan out signals and then place tens of decoupling caps. To make things worse, the IC sits on a socket that occupies 8x the area of the QFN (5mmx5mm). (The socket occupies much area but does not add significant parasitics; it is rated up to 75 GHz). On the same layer I cannot place components within a radius of ~7mm. The backside is restricted as well due to the mounting holes of the socket but at least I can use partial real estate on the back side. But I would need to via down for that. However, I could place 50% of the capacitors onto the thermal ground paddle that I also created underneath the chip on the backside.
Now I have read multiple times there should not be a via between the coupling cap and the pin. But what is worse? Via or longer wire?
In terms of inductance, a 7mm trace would be around 5-7nH (http://chemandy.com/calculators/flat-wire-inductor-calculator.htm). A 22mil diameter/10mil hole is far below 1nH (http://referencedesigner.com/rfcal/cal_13.php).