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This may "yet another" question about decoupling but the question is pretty precise and I can not find an answer.

I have a 40 pin QFN where I need to fan out signals and then place tens of decoupling caps. To make things worse, the IC sits on a socket that occupies 8x the area of the QFN (5mmx5mm). (The socket occupies much area but does not add significant parasitics; it is rated up to 75 GHz). On the same layer I cannot place components within a radius of ~7mm. The backside is restricted as well due to the mounting holes of the socket but at least I can use partial real estate on the back side. But I would need to via down for that. However, I could place 50% of the capacitors onto the thermal ground paddle that I also created underneath the chip on the backside.

Now I have read multiple times there should not be a via between the coupling cap and the pin. But what is worse? Via or longer wire?

In terms of inductance, a 7mm trace would be around 5-7nH (http://chemandy.com/calculators/flat-wire-inductor-calculator.htm). A 22mil diameter/10mil hole is far below 1nH (http://referencedesigner.com/rfcal/cal_13.php).

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  • \$\begingroup\$ If you have to compromise and use via's between decoupling and pin, you could also use multiple via's. Your'e talking about RF socket, but you did not mention the frequencies (analog) or typical rise times (digital) you're working with. \$\endgroup\$
    – gommer
    Jan 31, 2018 at 10:30
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    \$\begingroup\$ Is this a 6 layer board or greater? If so make your power layers tightly coupled. They will have a stronger decoupling effect then the physical capacitors. You can then place your caps further away and not have to worry to much. \$\endgroup\$
    – efox29
    Jan 31, 2018 at 11:56
  • \$\begingroup\$ It looks like they do an option without mounting holes, so that would give you back some real estate \$\endgroup\$
    – anon
    Jan 31, 2018 at 14:06
  • \$\begingroup\$ @efox29: That's an interesting point! It's still in the works and I can do "arbitrary" many layers. The issue: I have at least 6 voltages on board and the QFN chip in question uses two of them. The area is probably not too big. Could you elaborate how you would implement this? Which layer order, multiple supplies on one layer vs not, etc. \$\endgroup\$
    – divB
    Jan 31, 2018 at 20:47
  • \$\begingroup\$ @efox29: I just looked at the Altera PDN tool. It seems like the planes has to span the entire board (like 10000x10000 mil) to have effect. That's just not possible for me with so many supplies. \$\endgroup\$
    – divB
    Jan 31, 2018 at 21:37

2 Answers 2

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Don't stress too much its all about minimizing that inductance. That doesn't always translate into distance. If I were you I would take steps to minimize all the contributions to the total path inductance between the pin and the cap. You don't mention what speeds your chip is running at but you do say it's in a QFN. I only say that because sometimes we get obsessed with adding decoupling when the package itself is a limitation.

So how crazy do you want to get? Lets minimize each section. Starting with the caps you could pick a lower inductance package for example a 306 (603 turned sideways), 201s if you can get your values, MLCC caps, or there's an X2Y variant made for decoupling and RF-land.

Next the mounting strategy, if one via is good why not two. More parallel vias should be a lower impedance. If doing 0306, or 201 style caps make sure to do the via to the side trick, again trying to minimize loop area.

Ok so now I say put them on the top. Make part of your top layer a copper flood for the power side. Then on the next layer 5 mil or less below the top make that GND. Use multiple gnd vias at the socket pins. This will give you a nice low impedance path from the above caps into those pins. I did an analysis one time on HS section of an FPGA. A nice tight plane structure and caps like I described outperformed capacitors directly underneath the parts using multiple vias.

Finally if you want to feel better about it you could do some simulation or analysis. There's plenty of topics written about PDN design out there. If you don't have a simulator check out Altera's free PDN excel tool. The design guide has some really nice information in it.

I've used those sockets before they're pretty nice, and have also stressed about where to put caps.

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  • \$\begingroup\$ Great answer and the Aterra PDN tool is amazing! I have about 7 bias voltages (that also need decap) and 2 supplies into the small QFN (with socket) so you can imagine how crowded that is. Hence I via down the supplies immideatly (4 vias) and place decap very close at the bottom. The (less important) biases I via out with as thick wires as possible and put decap on the top, farther away. \$\endgroup\$
    – divB
    Feb 1, 2018 at 1:10
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I would say the via solution is the better one. However since you are using a socket I expect that the socket dictates (deteriorates) the overall performance (inductance to a decoupling capacitor) that in the end it probably doesn't matter what you do. The via or the long trace.

But if the via solution is acceptable (also regarding thermal issues) then I would choose that.

If the space is available you could also just place the pads in both places and then later decide or measure which solution is better.

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  • \$\begingroup\$ Maybe I should not have mentioned the socket but no, the socket does not limit the performance (it's a 700$ Ironwood elastomer socket that goes up to 76 GHz. It barely adds any parasitics). \$\endgroup\$
    – divB
    Jan 31, 2018 at 10:45
  • \$\begingroup\$ Both places will not work because the whole area is absolutely crowded no matter what. I could do one board with and one without socket. But that's what I would like to avoid. \$\endgroup\$
    – divB
    Jan 31, 2018 at 10:46
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    \$\begingroup\$ elastomer socket that goes up to 76 GHz OK, I pictured a real socket. But you're not using that. I know about elastomer socket type, uses them in the past. Then the socket's inductance will not be that large. I'd go for the via solution then. \$\endgroup\$
    – Bimpelrekkie
    Jan 31, 2018 at 10:54
  • \$\begingroup\$ The socket inductance of such sockets seems to be below 0.1nH according to Ironwood. Very interesting technology. I would optimize for low-inductance anyway. \$\endgroup\$
    – Manu3l0us
    Jan 31, 2018 at 11:23
  • \$\begingroup\$ @Manu3l0us The "socket" is more like a construction to hold/push/clamp the chip onto the PCB. Since that does not guarantee every pin will have a proper connection, an elastomer with conductive channels (gold wires) is placed between the PCB and the chip. These elastomers, although small (the size of the packaged chip), are very expensive and wear out after some time especially if you change the chip many times. \$\endgroup\$
    – Bimpelrekkie
    Jan 31, 2018 at 11:31

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