The datasheet says:


Because the DAC output voltage is controlled by the voltage monitor and control block (see Figure 42), it is important to power the DVCC pin before applying any voltage to the AVDD and AVSS pins; otherwise, the G1 and G2 transmission gates are at an undefined state. The ideal power-up sequence is in the following order: GND, SIG_GND, DAC_GND, DVCC, AVDD, AVSS, and then the digital inputs. The relative order of powering AVDD and AVSS is not important, provided that they are powered up after DVCC.

I can't see in the document any information about how much time after DVCC the other rails should rise up.

My question is: it's ok to power all the rails together (+12V and +3.3V come from LDO, -12V from ICL76660A) minimizing the time when G1 and G2 are in an undefined states, or it's mandatory to delay AVCC/AVSS? In such a case, what's the minimum delay needed?

Figure 43 shows an external circuit to delay AVdd but the text says:

C1, R2, and R3 are the main components that dictates the delay from DVCC enable to AVDD. Adjust the values according for the desired delay.

Well, I really haven't a desired delay... they seem to have one!


This is to prevent the dreaded CMOS SCR latchup effect from the inherent PNPN substrate. (search if you dont know about this)

Comparing the slew rate of Vdd vs speed of transistors Consider anything more than 1us after PS slew rate with Vdd = OK .

  • \$\begingroup\$ If I understand correctly the latch up is irreversible. I mean, if it happens due to an incorrect power up sequence, it will stay there and won't recovery by itself. For this reason it's mandatory to add even a small delay to AVdd. \$\endgroup\$ – Mark Jan 31 '18 at 14:22
  • \$\begingroup\$ Transistor delays will be << 1us. SCR's are latches until current drops below holding current.. ( power cycle) \$\endgroup\$ – Sunnyskyguy EE75 Jan 31 '18 at 14:25

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