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What I understand is, the ARM mode can execute 32-bit of instructions and Thumb mode can execute 16-bit of instructions.

For instance,

enter image description here

Here is the ARM instructions set:

enter image description here

And Thumb instructions set:

enter image description here

From these both instruction set tables, please see ADC mnemonic that describes add two 32-bit values and carry. So, 32-bit is common in both the modes.

What I didn't understand is, how a thumb mode which can execute 16-bit is able to execute 32-bit value?

I referred the other books (which I could) and in those books also same description is given. Please explain me this concept/correct me which I misunderstood.

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  • \$\begingroup\$ It still always reads and writes 32 bits per read or write instruction. Thumb mode simply means that 32-bit instruction read contains 2 instructions. That's all. \$\endgroup\$ – Brian Drummond Jan 31 '18 at 14:31
  • \$\begingroup\$ Why should a 16-bit instruction be unable to manipulate a 32-bit value? In English I can say "add the two 1000-digit numbers I just told you" in a lot fewer than 1000 letters. \$\endgroup\$ – user253751 Feb 1 '18 at 23:21
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The data bus width of the processor has nothing to do with the length of the instructions.

The ARM processor can manipulate 32 bit values because it is a 32-bit processor, whatever mode it is running in (Thumb or ARM). It just means its registers are 32 bits wide. And the registers don't change when you switch mode.

Now, it doesn't have any implication on the length of the instructions. The instructions could be encoded in any length. The x86, for example, uses 8-bit instructions but is also able to work on 32 bit values. For ARM, this is what changes when you switch to/from ARM and thumb modes.

For example, the instruction MOV R0, R1 (copy the contents of the 32-bit R1 register to the R0 register) is encoded in the following way:

  • E1A00001 for ARM (32 bit)
  • 4608 for Thumb (16-bit)

But the processor, in the end, will perform exactly the same operation, and it will do it on 32-bit wide data, whatever the mode.

This ability to switch modes simply allows you to decide on the compromise between code density and flexibility. You can pack more instructions in a kB of code with 16-bit instructions, but the 32 bit instructions are more flexible (they offer more features and you can do more with a single instruction).

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  • \$\begingroup\$ Quick followup: Is there benefits to swapping between ARM/Thumb modes? My understanding is that ARM mode may offer faster execution at the expense of code space. IF so, is it possible to execute in ARM mode in tight loops? \$\endgroup\$ – gregb212 Jan 31 '18 at 15:03
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    \$\begingroup\$ @gregb212 You are right. ARM execution is supposed to be faster, and, indeed, you can switch modes whenever it pleases you. But in reality, because Thumb packs more instructions in the same size, the data bus will be less crowded due to fetches, and cache misses will also be less likely. So, depending on the system architecture (if the memory is the bottleneck), Thumb could actually perform better than ARM. I think since Thumb2, the usage of 32-bit ARM instructions is dropping. \$\endgroup\$ – dim Jan 31 '18 at 15:09
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The canonical reference for this information is the ARM Architecture Reference Manual. The situation is complicated by there being many versions of this document, and many architectures. Generally, the most recent versions will be more complete in their formalisation (since there can now exist 16, 32 and 64 'flavours' which could be conflated).

For example, ARM DDI 0487C.a ARMv8, for ARMv8-A (edited)

The Execution states are:

AArch64 The 64-bit Execution state. This Execution state:

• Provides 31 64-bit general-purpose registers, of which X30 is used as the procedure link register.

• Provides a 64-bit program counter (PC), stack pointers (SPs), and exception link registers (ELRs).

• Provides a single instruction set, A64.

AArch32 The 32-bit Execution state. This Execution state:

• Provides 13 32-bit general-purpose registers, and a 32-bit PC, SP, and link register (LR). The LR is used as both an ELR and a procedure link register.

Some of these registers have multiple banked instances for use in different PE modes.

• Provides two instruction sets, A32 and T32.

In ARMv8 the possible instruction sets depend on the Execution state:

AArch64 AArch64 state supports only a single instruction set, called A64. This is a fixed-length instruction set that uses 32-bit instruction encodings.

AArch32 AArch32 state supports the following instruction sets:

A32 This is a fixed-length instruction set that uses 32-bit instruction encodings.

T32 This is a variable-length instruction set that uses both 16-bit and 32-bit instruction encodings.

In previous documentation, these instruction sets were called the ARM and Thumb instruction sets.

Critically, the A32 and T32 instruction sets are used within AArch32 where the general purpose registers are 32-bit. The T bit only affects the instruction decode, selecting between the 32 bit instruction set, or the mixed 16/32 bit instruction set.

It's also worth noting that any documentation which refers to Thumb being a 16 bit instruction set is very old. Assuming you are studying now, rather than working with an old design, the most restricted subset which is relevant is the ARMv6-M architecture, and the instruction set implemented by the Cortex-M0 processor.

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  • \$\begingroup\$ An answer worth a 1000 manuals. \$\endgroup\$ – not2qubit Oct 30 '18 at 4:06
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Thumb mode doesn't turn the ARM into a 16-bit CPU.

In Thumb mode, the CPU uses 16-bit instruction op-codes instead of 32-bit ones, to reduce program memory usage.

The registers, ALU and memory buses are still 32-bit.

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  • \$\begingroup\$ You could be explicit here, and say 'code memory usage'. Of course, it's not a 50% saving since the shorter instructions are less expressive (for example, a single instruction with condition is 2x16 bit instructions) \$\endgroup\$ – Sean Houlihane Feb 1 '18 at 19:16
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    \$\begingroup\$ @SeanHoulihane, I'd rather not give a long over-detailed explanation that hides the simplicity of the point from the OP. Plenty out there if they want to read further. \$\endgroup\$ – TonyM Feb 1 '18 at 19:29
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Roughly speaking, a CPU instruction is a particular sequence of bits which, when presented to the CPU, means "Add two 32-bit values and carry". The exact value of bits in this sequence has nothing to do with values being added.

In 32-bit instruction set, this sequence is composed of 32 bits. In thumb, it only has 16. Obviously, thumb has less instructions (because there's less bits to encode them), but instructions which are implemented do exactly the same thing in both instruction sets.

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Thumb-1 only does 16 bit instructions while Thumb-2 processors can do both 16 & 32bit both sharing same architecture for 32 bit data. So one would expect both to share same data bus since only the instruction registers are changing.

Moving up to 64 Bit processors, Thumb can support both 32 & 64 bit instructions with some different in each set in order to conserve code space for some applications but at the expense of duplicate libraries.

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