Why are the 2 outputs of SR flipflop using nor gates considered to be Q and Q'? If we consider them Q and P for eg. The configuration S=1 and R=1 would be valid. So why are they considered complimentary of each other. They are clearly not complimentary since one configuration does not match the truth table of negation
Except in the case where S = R = 1, the two outputs are opposite. That's why we say the two outputs are Q and Q'. The question then becomes "why is S = R = 1 illegal?"
The picture above shows a NOR SR latch with S = R = 1. Notice how the outputs are both 0 since 1 NOR anything = 0 (the program I am using is Logisim, by the way). If I then set the inputs back to the quiescent state where S = R = 0 (which is supposed to keep the state of the latch since 0 NOR x means the output depends SOLELY on x (0 NOR 0 = 1, 0 NOR 1 = 0, where the first 0 does not give us enough information to determine the output the same way 1 NOR x does)). X in this case is the output of the other NOR gate, so if the two inputs S and R are both 0, they do not affect the outputs, thus the state is "latched."
Anyway, when S = R = 1, A and B (top and bottom outputs) are both 0. What would happen if we switch S and R back to 0? A then becomes 0 NOR B, but remember that B was 0 before we change S and R back to being 0, so A = 0 NOR B = 0 NOR 0 = 1, and B = 0 NOR A = 0 NOR 1 = 0.
But, what would happen if B switched first? Then, B = 0 NOR A = 0 NOR 0 = 1, and A = 0 NOR B = 0 NOR 1 = 0.
The point is that, depending on which output changes first, we can not tell whether A = 1 and B = 0 or if A = 0 and B = 1. It depends on which output, A or B, changes first, and if we reset S and R back to 0 at the same time, it is completely random.
That's why S = R = 1 is illegal in a NOR SR latch, which is why, for all legal inputs, A and B are inverses, or as you'll see it, A = Q and B = Q'.
EDIT: For the sake of completion, I included pictures of all other states:
The outputs Q and Q' are complementary of each other as long as the configuration S=R=1 is not allowed. This is called a forbidden state as both NOR gates output zeros. This negates the logical equation Q=Q'. Therefore this state is not allowed.
So for a NOR SR latch the outputs are complementary to each other as long as the forbidden state S=R=1 is not considered.
Now there is another problem with this forbidden state that makes it even more inappropriate in circuits. When a forbidden to hold transition takes place due to a problem known as race condition the output Q may lock to either 1 or 0, depending on the propagation delays between the gates. So that is one more reason to avoid this situation even if you may be interested in this configuration.
There are some solutions to overcome this problem occurring with SR latch. One is to consider a JK flip flop in which the configuration (J,K)=(1,1) is no longer restricted. There are still other solutions to convert this restricted state to a non-restricted state which I leave it to you as an exercise.