The SOA also shows the power curve for various time durations. It is essential for you to understand that your failure is from excess internal power ( CTE stress) and not excess temperature. The difference is the stress is much higher from internal sources with thermal gradients across the multi-layer chip on a rigid substrate encapsulated in a plastic package.
So give the SOA some slack and keep away from it. But pulse it 100A is ok 0.1A at 20V is too close to SOA limit at DC.
YOu cannot calculate max egress heat power based on Rthjc. ALthough it applies in both directions, the stress is significantly higher for egress and is intended to be used with ingress as well . So please understand SOA is a power density egresss limit and Rthjc technically, both ingress and egress so you can size your heatsink to limit Tj at max Tamb. and max power.
Thermal gradients create non-linear stress limits guided by the SOA and depend on pulse duration. It is not wise to design it for normal operation near these limits as other environmental factors may apply.
Also those curves are typical and not worst case. So although you were just inside the lower RIGHT BOTTOM corner of the SOA, you did not apply any margin to your design.
It is like designing a roof that will fail at 1 ton and using it at 0.9 ton and wondering why it failed. Architects use big safety factors for typical specs for such failure mode.
EE designers need to learn prudent design margins by experience, since there is no written code for every limit. That's what corporate standards or mentors are for. I use 20~25% margin in my designs but sometimes more and I would never allow the junction to exceed 125'C at max power at maximum ambient unless there was a reason like high internal ambient from other heat sources. then I may consider 140'C at worst case for a MOSFET under rare circumstances even though it can run at 175'C. That is personal designer's choice for safety margin.
But when I qualified OEM products for a large corporation we verified every design including hotspots and would not permit any above 125'C at room temp, which is a looser than my worst case design.
The case will NOT get hot in 1 second when it fails.
Arhnenius law's for chemistry and component failure rates dictate you can improve life time by 50% for every 10deg C drop in junction temp.
In your case it was not junction temp but a non-linear thermal stress crack caused by being too close to the SOA limit.
Also keep in mind that plastic parts are not perfect seals and prolonged exposure to high %RH and operation well above boiling point can create thermal stress from micro-steam or pop-corn effect. THis is normally a high risk for LEDs and parts that must be sealed from factory till a few days or same day of soldering depending on %RH.
In this case the risk is low but still an added stresser for %RH may account for your failure just within the SOA.