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I am trying to use an IPP114N03L G (datasheet).

I calculated the maximum power it could handle as follows:

From the first two pages of the datasheet: Rthjc = 3.9K/W Tj(max) = 175C

Assuming I can keep the case under 50C, max. power dissipation should be: (175 - 50) / 3.9 = 32W

So 1A at 30V should be about the maximum.

Now looking at the Safe Operating Area graph on page 4, at 30V it says ~150mA max. and that is with Tc at only 25C.

Why do these figures disagree?

In practice, I have killed two of these devices now, the last one was at around 20V 200mA, so it seems the first calculation is wrong. The case was cool.

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  • \$\begingroup\$ What kind of heat sink are you using? Is that 20V 200mA continuous? \$\endgroup\$ – W5VO Jul 9 '12 at 13:53
  • \$\begingroup\$ It's screwed onto a CPU heatsink and fan, with arctic silver thermal paste. Probably overkill but it's what I had around. In any case it felt cool. "Continuous" very breifly before it died. \$\endgroup\$ – river Jul 9 '12 at 14:08
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ipp114n03l soa

The SOA for this FET shows an additional limitation (beyond the traditional Vds, Imax, Rds, and P lines), that is not commonly found in other MOSFETs: the lines under the 10 ms and 1 ms markers. The only possible reason for this limitation that I found appears on the last page of IXYS Power MOSFET Datasheet Parameters Definition:

" These theoretical constant power curves are derived from calculation with assumption of essentially uniform junction temperature across the Power MOSFET die. This assumption is not always valid, especially for a large die MOSFETs. ...(more explanation)... Modern Power MOSFETs optimized for a switch-mode applications were found to have limited capability to operate in the right-side bottom corner of the FBSOA graph."

Note that this transistor is intended for switching, not for linear operation, so it is probably optimized for that task: it is not designed for operating for longer time in this lower-right corner of the SOA. Note also that for small times (< 10us, as occur in switching) there is essentially no such lower-right-hand-corner limitation.

For comparison: the SOA of a random MSOFET (irf7146):irf7416 SOA

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  • \$\begingroup\$ I have already allowed for maximum voltage, current, power and temperature. Second breakdown is a phenomenon which only occurs in BJTs, not MOSFETs. Is there some other limitation I don't know about? \$\endgroup\$ – river Jul 9 '12 at 14:05
  • \$\begingroup\$ I think the OP is asking why there is a steep region on the SOAR curve (fig 3) between constant power of Pdmax (38W) and constant voltage of Vdsmax (30V) which doesn't seem to be explained by the figures in the datasheet. \$\endgroup\$ – MikeJ-UK Jul 9 '12 at 14:22
  • \$\begingroup\$ Thanks Mike, after some seqarching I updated my anwser with what seems to me the most probable reason (the datasheet does not state one). \$\endgroup\$ – Wouter van Ooijen Jul 9 '12 at 15:07
  • \$\begingroup\$ +1 - That would seem to be the explanation - and new to me!. \$\endgroup\$ – MikeJ-UK Jul 9 '12 at 15:13
  • \$\begingroup\$ New to me too, but after some googling... There is also the "avalanche effect" that is hinted to in various SOA-related texts, but that does not seem to be the limiting factor in this particular case. \$\endgroup\$ – Wouter van Ooijen Jul 9 '12 at 15:46
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The SOA also shows the power curve for various time durations. It is essential for you to understand that your failure is from excess internal power ( CTE stress) and not excess temperature. The difference is the stress is much higher from internal sources with thermal gradients across the multi-layer chip on a rigid substrate encapsulated in a plastic package.

So give the SOA some slack and keep away from it. But pulse it 100A is ok 0.1A at 20V is too close to SOA limit at DC.

YOu cannot calculate max egress heat power based on Rthjc. ALthough it applies in both directions, the stress is significantly higher for egress and is intended to be used with ingress as well . So please understand SOA is a power density egresss limit and Rthjc technically, both ingress and egress so you can size your heatsink to limit Tj at max Tamb. and max power.

Thermal gradients create non-linear stress limits guided by the SOA and depend on pulse duration. It is not wise to design it for normal operation near these limits as other environmental factors may apply.

Also those curves are typical and not worst case. So although you were just inside the lower RIGHT BOTTOM corner of the SOA, you did not apply any margin to your design.

It is like designing a roof that will fail at 1 ton and using it at 0.9 ton and wondering why it failed. Architects use big safety factors for typical specs for such failure mode.

EE designers need to learn prudent design margins by experience, since there is no written code for every limit. That's what corporate standards or mentors are for. I use 20~25% margin in my designs but sometimes more and I would never allow the junction to exceed 125'C at max power at maximum ambient unless there was a reason like high internal ambient from other heat sources. then I may consider 140'C at worst case for a MOSFET under rare circumstances even though it can run at 175'C. That is personal designer's choice for safety margin.

But when I qualified OEM products for a large corporation we verified every design including hotspots and would not permit any above 125'C at room temp, which is a looser than my worst case design.

The case will NOT get hot in 1 second when it fails.

Arhnenius law's for chemistry and component failure rates dictate you can improve life time by 50% for every 10deg C drop in junction temp.

In your case it was not junction temp but a non-linear thermal stress crack caused by being too close to the SOA limit.

Also keep in mind that plastic parts are not perfect seals and prolonged exposure to high %RH and operation well above boiling point can create thermal stress from micro-steam or pop-corn effect. THis is normally a high risk for LEDs and parts that must be sealed from factory till a few days or same day of soldering depending on %RH.

In this case the risk is low but still an added stresser for %RH may account for your failure just within the SOA.

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    \$\begingroup\$ CTE: Coefficient of Thermal Expansion. That probably explains the quiet pop I heard when the first one died. A cracking die maybe. \$\endgroup\$ – river Jul 9 '12 at 16:57
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    \$\begingroup\$ I'm not sure what you mean by ingress and egress. Do you mean that an increase in ambient temperature (ingress heat) will cause a fairly even heating internally, so no thermal stress problem, but an increase in internally generated heat, which then egresses, is a problem because of the heat being concentrated at a point giving a higher temperature variation on the die, causing thermal stress cracks? \$\endgroup\$ – river Jul 9 '12 at 17:00
  • \$\begingroup\$ Correct... Egress and Ingress are common terms of stress or leakage that also applies to EMI in both directions. \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Jul 9 '12 at 22:51
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What you mention may have to do with thermal runaway, sometimes referred to as the Spirito effect.

For linear mode operation with low VGS, MOSFETs may be prone to thermal runaway.

See also this related answer: https://electronics.stackexchange.com/a/36625/930

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