How to use the parameter in comparing the variable and constant value?

Question

I've learned that using a parameter in defining a module is a good habit like having a default value for the parameter in C++ or other languages.

So, I've used a parameter value a lot but faced a problem when I want to compare some register variable to a constant value that has an equal size with the parameter.

For example, I declare a variable size of which is the value of the parameter and would like to compare it with a constant value sized 8bits such as 8'b0.

module top_module #(parameter SIZE = 8) (output out_top);
  reg [(SIZE-1):0] temp_var;
  assign out_top = (temp_var == 8'b0) ? 1'b0 : 1'b1;
endmodule   

If I use the constant value with the specific size, in this case, 8'b, it would be problematic when I want to instantiate the module with the #SIZE = 16 like below.

top_module #(SIZE=16) top_module_inst;

Is there any way to use the parameter in a declaration of the parameter?

Or should I change the size of the constant value when I instantiate the module with different size every time?

Can anyone please explain the differences between using Hardcoded values and parameters during Synthesis and Simulation?

Answer 1

The verilog replication operator will work here.

The general syntax is: {n{m}} (m will be replicated n times).

The replication count, n, must be a constant value, and can be a parameter value.

In your case, the code would be:

assign out_top = (temp_var == { SIZE {1'b0} } ) ? 1b'0 : 1'b1;